Merge "msm: clock-8084: Change the halt check type for UFS and PCIE clocks" (fadb9ded) · Commits · e / devices / android_kernel_sony_msm8994

arch/arm/mach-msm/clock-8084.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -2722,6 +2722,7 @@ static struct branch_clk gcc_pcie_0_pipe_clk = {
		.cbcr_reg = PCIE_0_PIPE_CBCR,
		.has_sibling = 0,
		.base = &virt_bases[GCC_BASE],
		.halt_check = DELAY,
		.c = {
		.parent = &pcie_0_pipe_clk_src.c,
		.dbg_name = "gcc_pcie_0_pipe_clk",
		@@ -2779,6 +2780,7 @@ static struct branch_clk gcc_pcie_1_pipe_clk = {
		.cbcr_reg = PCIE_1_PIPE_CBCR,
		.has_sibling = 0,
		.base = &virt_bases[GCC_BASE],
		.halt_check = DELAY,
		.c = {
		.parent = &pcie_1_pipe_clk_src.c,
		.dbg_name = "gcc_pcie_1_pipe_clk",
		@@ -3139,6 +3141,7 @@ static struct branch_clk gcc_ufs_rx_cfg_clk = {
		static struct branch_clk gcc_ufs_rx_symbol_0_clk = {
		.cbcr_reg = UFS_RX_SYMBOL_0_CBCR,
		.base = &virt_bases[GCC_BASE],
		.halt_check = DELAY,
		.c = {
		.dbg_name = "gcc_ufs_rx_symbol_0_clk",
		.ops = &clk_ops_branch,
		@@ -3149,6 +3152,7 @@ static struct branch_clk gcc_ufs_rx_symbol_0_clk = {
		static struct branch_clk gcc_ufs_rx_symbol_1_clk = {
		.cbcr_reg = UFS_RX_SYMBOL_1_CBCR,
		.base = &virt_bases[GCC_BASE],
		.halt_check = DELAY,
		.c = {
		.dbg_name = "gcc_ufs_rx_symbol_1_clk",
		.ops = &clk_ops_branch,
		@@ -3173,6 +3177,7 @@ static struct branch_clk gcc_ufs_tx_cfg_clk = {
		static struct branch_clk gcc_ufs_tx_symbol_0_clk = {
		.cbcr_reg = UFS_TX_SYMBOL_0_CBCR,
		.base = &virt_bases[GCC_BASE],
		.halt_check = DELAY,
		.c = {
		.dbg_name = "gcc_ufs_tx_symbol_0_clk",
		.ops = &clk_ops_branch,
		@@ -3183,6 +3188,7 @@ static struct branch_clk gcc_ufs_tx_symbol_0_clk = {
		static struct branch_clk gcc_ufs_tx_symbol_1_clk = {
		.cbcr_reg = UFS_TX_SYMBOL_1_CBCR,
		.base = &virt_bases[GCC_BASE],
		.halt_check = DELAY,
		.c = {
		.dbg_name = "gcc_ufs_tx_symbol_1_clk",
		.ops = &clk_ops_branch,