Loading Documentation/devicetree/bindings/ufs/ufs-msm.txt +7 −3 Original line number Diff line number Diff line Loading @@ -7,8 +7,11 @@ To bind UFS PHY with UFS host controller, the controller node should contain a phandle reference to UFS PHY node. Required properties: - compatible : compatible list, contains "qcom,ufsphy" - compatible : compatible list, contains "qcom,ufs-msm-phy-qmp-28nm" or "qcom,ufs-msm-phy-qmp-20nm" according to the relevant phy in use - reg : <registers mapping> - #phy-cells : This property shall be set to 0 - vdda-phy-supply : phandle to main PHY supply for analog domain - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply Loading @@ -19,8 +22,9 @@ Optional properties: Example: ufsphy1: ufsphy@0xfc597000 { compatible = "qcom,ufsphy"; compatible = "qcom,ufs-msm-phy-qmp-28nm"; reg = <0xfc597000 0x800>; #phy-cells = <0>; vdda-phy-supply = <&pma8084_l4>; vdda-pll-supply = <&pma8084_l12>; vdda-phy-max-microamp = <50000>; Loading @@ -29,5 +33,5 @@ Example: ufshc@0xfc598000 { ... ufs-phy = <&ufsphy1>; phys = <&ufsphy1>; }; Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +1 −1 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ Required properties: - reg : <registers mapping> Optional properties: - ufs-phy : phandle to UFS PHY node - phys : phandle to UFS PHY node - vdd-hba-supply : phandle to UFS host controller supply regulator node - vcc-supply : phandle to VCC supply regulator node - vccq-supply : phandle to VCCQ supply regulator node Loading arch/arm/boot/dts/qcom/apq8084.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -4656,8 +4656,9 @@ }; ufsphy1: ufsphy@0xfc597000 { compatible = "qcom,ufsphy"; compatible = "qcom,ufs-msm-phy-qmp-28nm"; reg = <0xfc597000 0x87c>; #phy-cells = <0>; vdda-phy-supply = <&pma8084_l3>; vdda-pll-supply = <&pma8084_l12>; vdda-phy-max-microamp = <50000>; Loading @@ -4670,8 +4671,7 @@ compatible = "qcom,ufshc"; reg = <0xfc594000 0x800>; interrupts = <0 28 0>; ufs-phy = <&ufsphy1>; phys = <&ufsphy1>; vcc-supply = <&pma8084_l19>; vccq-supply = <&pma8084_l4>; vccq2-supply = <&pma8084_s4>; Loading arch/arm/boot/dts/qcom/msm8994.dtsi +13 −10 Original line number Diff line number Diff line Loading @@ -937,16 +937,19 @@ }; ufsphy1: ufsphy@fc597000 { compatible = "qcom,ufsphy"; compatible = "qcom,ufs-msm-phy-qmp-20nm"; reg = <0xfc597000 0xda8>; #phy-cells = <0>; vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; vdda-phy-max-microamp = <45000>; vdda-pll-max-microamp = <100>; clock-names = "ref_clk_src", "ref_clk_parent", "ref_clk", "tx_iface_clk", clock-names = "ref_clk_src", "ref_clk_parent", "ref_clk", "tx_iface_clk", "rx_iface_clk"; clocks = <&clock_rpm clk_ln_bb_clk>, clocks = <&clock_rpm clk_ln_bb_clk>, <&clock_gcc clk_pcie_1_phy_ldo >, <&clock_gcc clk_ufs_phy_ldo>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, Loading @@ -958,7 +961,7 @@ compatible = "qcom,ufshc"; reg = <0xfc594000 0x2500>; interrupts = <0 265 0>; ufs-phy = <&ufsphy1>; phys = <&ufsphy1>; vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pm8994_l20>; Loading drivers/scsi/ufs/Makefile +3 −0 Original line number Diff line number Diff line # UFSHCD makefile obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm.o obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm-phy.o obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm-phy-qmp-28nm.o obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm-phy-qmp-20nm.o obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o ufs_quirks.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o Loading Loading
Documentation/devicetree/bindings/ufs/ufs-msm.txt +7 −3 Original line number Diff line number Diff line Loading @@ -7,8 +7,11 @@ To bind UFS PHY with UFS host controller, the controller node should contain a phandle reference to UFS PHY node. Required properties: - compatible : compatible list, contains "qcom,ufsphy" - compatible : compatible list, contains "qcom,ufs-msm-phy-qmp-28nm" or "qcom,ufs-msm-phy-qmp-20nm" according to the relevant phy in use - reg : <registers mapping> - #phy-cells : This property shall be set to 0 - vdda-phy-supply : phandle to main PHY supply for analog domain - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply Loading @@ -19,8 +22,9 @@ Optional properties: Example: ufsphy1: ufsphy@0xfc597000 { compatible = "qcom,ufsphy"; compatible = "qcom,ufs-msm-phy-qmp-28nm"; reg = <0xfc597000 0x800>; #phy-cells = <0>; vdda-phy-supply = <&pma8084_l4>; vdda-pll-supply = <&pma8084_l12>; vdda-phy-max-microamp = <50000>; Loading @@ -29,5 +33,5 @@ Example: ufshc@0xfc598000 { ... ufs-phy = <&ufsphy1>; phys = <&ufsphy1>; };
Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +1 −1 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ Required properties: - reg : <registers mapping> Optional properties: - ufs-phy : phandle to UFS PHY node - phys : phandle to UFS PHY node - vdd-hba-supply : phandle to UFS host controller supply regulator node - vcc-supply : phandle to VCC supply regulator node - vccq-supply : phandle to VCCQ supply regulator node Loading
arch/arm/boot/dts/qcom/apq8084.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -4656,8 +4656,9 @@ }; ufsphy1: ufsphy@0xfc597000 { compatible = "qcom,ufsphy"; compatible = "qcom,ufs-msm-phy-qmp-28nm"; reg = <0xfc597000 0x87c>; #phy-cells = <0>; vdda-phy-supply = <&pma8084_l3>; vdda-pll-supply = <&pma8084_l12>; vdda-phy-max-microamp = <50000>; Loading @@ -4670,8 +4671,7 @@ compatible = "qcom,ufshc"; reg = <0xfc594000 0x800>; interrupts = <0 28 0>; ufs-phy = <&ufsphy1>; phys = <&ufsphy1>; vcc-supply = <&pma8084_l19>; vccq-supply = <&pma8084_l4>; vccq2-supply = <&pma8084_s4>; Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +13 −10 Original line number Diff line number Diff line Loading @@ -937,16 +937,19 @@ }; ufsphy1: ufsphy@fc597000 { compatible = "qcom,ufsphy"; compatible = "qcom,ufs-msm-phy-qmp-20nm"; reg = <0xfc597000 0xda8>; #phy-cells = <0>; vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; vdda-phy-max-microamp = <45000>; vdda-pll-max-microamp = <100>; clock-names = "ref_clk_src", "ref_clk_parent", "ref_clk", "tx_iface_clk", clock-names = "ref_clk_src", "ref_clk_parent", "ref_clk", "tx_iface_clk", "rx_iface_clk"; clocks = <&clock_rpm clk_ln_bb_clk>, clocks = <&clock_rpm clk_ln_bb_clk>, <&clock_gcc clk_pcie_1_phy_ldo >, <&clock_gcc clk_ufs_phy_ldo>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, Loading @@ -958,7 +961,7 @@ compatible = "qcom,ufshc"; reg = <0xfc594000 0x2500>; interrupts = <0 265 0>; ufs-phy = <&ufsphy1>; phys = <&ufsphy1>; vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; vcc-supply = <&pm8994_l20>; Loading
drivers/scsi/ufs/Makefile +3 −0 Original line number Diff line number Diff line # UFSHCD makefile obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm.o obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm-phy.o obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm-phy-qmp-28nm.o obj-$(CONFIG_SCSI_UFS_MSM) += ufs-msm-phy-qmp-20nm.o obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o ufs_quirks.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o Loading