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Commit f800a430 authored by Vikram Mulukutla's avatar Vikram Mulukutla
Browse files

qcom: clock-cpu-8994: Add lock bit masks 



The A53/A57 PLLs have lock bits located in different registers.
Add support for them.

Change-Id: I7b7fb0bf0cf45c9ae03da547e8153127249649ef
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent d01adbbd

drivers/clk/qcom/clock-cpu-8994.c

+8 −4
Original line number Diff line number Diff line
@@ -148,7 +148,7 @@ static struct pll_clk a57_pll0 = { 
	.alpha_reg = (void __iomem *)C1_PLL_ALPHA,

	.config_reg = (void __iomem *)C1_PLL_USER_CTL,

	.config_ctl_reg = (void __iomem *)C1_PLL_CONFIG_CTL,

	.status_reg = (void __iomem *)C1_PLL_STATUS,

	.status_reg = (void __iomem *)C1_PLL_MODE,

	.masks = {

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),
@@ -156,6 +156,7 @@ static struct pll_clk a57_pll0 = { 
		.main_output_mask = BIT(0),

		.early_output_mask = BIT(3),

		.apc_pdn_mask = BIT(24),

		.lock_mask = BIT(31),

	},

	.vals = {

		.post_div_masked = 0x100,
@@ -180,7 +181,7 @@ static struct pll_clk a57_pll1 = { 
	.alpha_reg = (void __iomem *)C1_PLLA_ALPHA,

	.config_reg = (void __iomem *)C1_PLLA_USER_CTL,

	.config_ctl_reg = (void __iomem *)C1_PLLA_CONFIG_CTL,

	.status_reg = (void __iomem *)C1_PLLA_STATUS,

	.status_reg = (void __iomem *)C1_PLLA_MODE,

	.masks = {

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),
@@ -188,6 +189,7 @@ static struct pll_clk a57_pll1 = { 
		.main_output_mask = BIT(0),

		.early_output_mask = BIT(3),

		.apc_pdn_mask = BIT(24),

		.lock_mask = BIT(31),

	},

	.vals = {

		.post_div_masked = 0x300,
@@ -214,7 +216,7 @@ static struct pll_clk a53_pll0 = { 
	.alpha_reg = (void __iomem *)C0_PLL_ALPHA,

	.config_reg = (void __iomem *)C0_PLL_USER_CTL,

	.config_ctl_reg = (void __iomem *)C0_PLL_CONFIG_CTL,

	.status_reg = (void __iomem *)C0_PLL_STATUS,

	.status_reg = (void __iomem *)C0_PLL_MODE,

	.masks = {

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),
@@ -222,6 +224,7 @@ static struct pll_clk a53_pll0 = { 
		.main_output_mask = BIT(0),

		.early_output_mask = BIT(3),

		.apc_pdn_mask = BIT(24),

		.lock_mask = BIT(31),

	},

	.vals = {

		.post_div_masked = 0x100,
@@ -246,7 +249,7 @@ static struct pll_clk a53_pll1 = { 
	.alpha_reg = (void __iomem *)C0_PLLA_ALPHA,

	.config_reg = (void __iomem *)C0_PLLA_USER_CTL,

	.config_ctl_reg = (void __iomem *)C0_PLLA_CONFIG_CTL,

	.status_reg = (void __iomem *)C0_PLLA_STATUS,

	.status_reg = (void __iomem *)C0_PLLA_MODE,

	.masks = {

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),
@@ -254,6 +257,7 @@ static struct pll_clk a53_pll1 = { 
		.main_output_mask = BIT(0),

		.early_output_mask = BIT(3),

		.apc_pdn_mask = BIT(24),

		.lock_mask = BIT(31),

	},

	.vals = {

		.post_div_masked = 0x300,