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Commit f770d78a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: halt engines before disabling MC (si) 



It's better to halt the engines before we disable the MC.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 90fb8779

drivers/gpu/drm/radeon/si.c

+7 −5
Original line number Diff line number Diff line
@@ -2220,11 +2220,6 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 
	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));



	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
@@ -2241,6 +2236,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 
		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

	}



	udelay(50);



	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {

		grbm_soft_reset = SOFT_RESET_CB |

			SOFT_RESET_DB |