Loading arch/arm/boot/compressed/head.S +10 −4 Original line number Diff line number Diff line Loading @@ -717,6 +717,9 @@ __armv7_mmu_cache_off: bl __armv7_mmu_cache_flush mov r0, #0 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB mov pc, r12 __arm6_mmu_cache_off: Loading Loading @@ -778,12 +781,13 @@ __armv6_mmu_cache_flush: __armv7_mmu_cache_flush: mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) beq hierarchical mov r10, #0 beq hierarchical mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D b iflush hierarchical: stmfd sp!, {r0-r5, r7, r9-r11} mcr p15, 0, r10, c7, c10, 5 @ DMB stmfd sp!, {r0-r5, r7, r9, r11} mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field Loading Loading @@ -820,12 +824,14 @@ skip: cmp r3, r10 bgt loop1 finished: ldmfd sp!, {r0-r5, r7, r9, r11} mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr ldmfd sp!, {r0-r5, r7, r9-r11} iflush: mcr p15, 0, r10, c7, c10, 4 @ DSB mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB mcr p15, 0, r10, c7, c10, 4 @ drain WB mcr p15, 0, r10, c7, c10, 4 @ DSB mcr p15, 0, r10, c7, c5, 4 @ ISB mov pc, lr __armv5tej_mmu_cache_flush: Loading arch/arm/include/asm/cacheflush.h +26 −10 Original line number Diff line number Diff line Loading @@ -15,6 +15,7 @@ #include <asm/glue.h> #include <asm/shmparam.h> #include <asm/cachetype.h> #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) Loading Loading @@ -295,16 +296,6 @@ static inline void outer_flush_range(unsigned long start, unsigned long end) #endif /* * flush_cache_vmap() is used when creating mappings (eg, via vmap, * vmalloc, ioremap etc) in kernel space for pages. Since the * direct-mappings of these pages may contain cached data, we need * to do a full cache flush to ensure that writebacks don't corrupt * data placed into these pages via the new mappings. */ #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() /* * Copy user data from/to a page which is mapped into a different * processes address space. Really, we want to allow our "user Loading Loading @@ -444,4 +435,29 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, dmac_inv_range(start, start + size); } /* * flush_cache_vmap() is used when creating mappings (eg, via vmap, * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT * caches, since the direct-mappings of these pages may contain cached * data, we need to do a full cache flush to ensure that writebacks * don't corrupt data placed into these pages via the new mappings. */ static inline void flush_cache_vmap(unsigned long start, unsigned long end) { if (!cache_is_vipt_nonaliasing()) flush_cache_all(); else /* * set_pte_at() called from vmap_pte_range() does not * have a DSB after cleaning the cache line. */ dsb(); } static inline void flush_cache_vunmap(unsigned long start, unsigned long end) { if (!cache_is_vipt_nonaliasing()) flush_cache_all(); } #endif arch/arm/include/asm/hwcap.h +1 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,7 @@ #define HWCAP_IWMMXT 512 #define HWCAP_CRUNCH 1024 #define HWCAP_THUMBEE 2048 #define HWCAP_NEON 4096 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) /* Loading arch/arm/kernel/setup.c +2 −0 Original line number Diff line number Diff line Loading @@ -772,6 +772,8 @@ static const char *hwcap_str[] = { "java", "iwmmxt", "crunch", "thumbee", "neon", NULL }; Loading arch/arm/kernel/thumbee.c +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ /* * Access to the ThumbEE Handler Base register */ static inline unsigned long teehbr_read() static inline unsigned long teehbr_read(void) { unsigned long v; asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v)); Loading Loading
arch/arm/boot/compressed/head.S +10 −4 Original line number Diff line number Diff line Loading @@ -717,6 +717,9 @@ __armv7_mmu_cache_off: bl __armv7_mmu_cache_flush mov r0, #0 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB mov pc, r12 __arm6_mmu_cache_off: Loading Loading @@ -778,12 +781,13 @@ __armv6_mmu_cache_flush: __armv7_mmu_cache_flush: mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) beq hierarchical mov r10, #0 beq hierarchical mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D b iflush hierarchical: stmfd sp!, {r0-r5, r7, r9-r11} mcr p15, 0, r10, c7, c10, 5 @ DMB stmfd sp!, {r0-r5, r7, r9, r11} mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field Loading Loading @@ -820,12 +824,14 @@ skip: cmp r3, r10 bgt loop1 finished: ldmfd sp!, {r0-r5, r7, r9, r11} mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr ldmfd sp!, {r0-r5, r7, r9-r11} iflush: mcr p15, 0, r10, c7, c10, 4 @ DSB mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB mcr p15, 0, r10, c7, c10, 4 @ drain WB mcr p15, 0, r10, c7, c10, 4 @ DSB mcr p15, 0, r10, c7, c5, 4 @ ISB mov pc, lr __armv5tej_mmu_cache_flush: Loading
arch/arm/include/asm/cacheflush.h +26 −10 Original line number Diff line number Diff line Loading @@ -15,6 +15,7 @@ #include <asm/glue.h> #include <asm/shmparam.h> #include <asm/cachetype.h> #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) Loading Loading @@ -295,16 +296,6 @@ static inline void outer_flush_range(unsigned long start, unsigned long end) #endif /* * flush_cache_vmap() is used when creating mappings (eg, via vmap, * vmalloc, ioremap etc) in kernel space for pages. Since the * direct-mappings of these pages may contain cached data, we need * to do a full cache flush to ensure that writebacks don't corrupt * data placed into these pages via the new mappings. */ #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() /* * Copy user data from/to a page which is mapped into a different * processes address space. Really, we want to allow our "user Loading Loading @@ -444,4 +435,29 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, dmac_inv_range(start, start + size); } /* * flush_cache_vmap() is used when creating mappings (eg, via vmap, * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT * caches, since the direct-mappings of these pages may contain cached * data, we need to do a full cache flush to ensure that writebacks * don't corrupt data placed into these pages via the new mappings. */ static inline void flush_cache_vmap(unsigned long start, unsigned long end) { if (!cache_is_vipt_nonaliasing()) flush_cache_all(); else /* * set_pte_at() called from vmap_pte_range() does not * have a DSB after cleaning the cache line. */ dsb(); } static inline void flush_cache_vunmap(unsigned long start, unsigned long end) { if (!cache_is_vipt_nonaliasing()) flush_cache_all(); } #endif
arch/arm/include/asm/hwcap.h +1 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,7 @@ #define HWCAP_IWMMXT 512 #define HWCAP_CRUNCH 1024 #define HWCAP_THUMBEE 2048 #define HWCAP_NEON 4096 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) /* Loading
arch/arm/kernel/setup.c +2 −0 Original line number Diff line number Diff line Loading @@ -772,6 +772,8 @@ static const char *hwcap_str[] = { "java", "iwmmxt", "crunch", "thumbee", "neon", NULL }; Loading
arch/arm/kernel/thumbee.c +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ /* * Access to the ThumbEE Handler Base register */ static inline unsigned long teehbr_read() static inline unsigned long teehbr_read(void) { unsigned long v; asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v)); Loading