Loading arch/arm/boot/dts/qcom/msm8994.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -2416,6 +2416,23 @@ status = "disabled"; }; dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9904000 0x19000>; interrupts = <0 238 0>; qcom,summing-threshold = <10>; }; dma_blsp2: qcom,sps-dma@f9944000 { /* BLSP2 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9944000 0x19000>; interrupts = <0 239 0>; qcom,summing-threshold = <10>; }; i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -2416,6 +2416,23 @@ status = "disabled"; }; dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9904000 0x19000>; interrupts = <0 238 0>; qcom,summing-threshold = <10>; }; dma_blsp2: qcom,sps-dma@f9944000 { /* BLSP2 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9944000 0x19000>; interrupts = <0 239 0>; qcom,summing-threshold = <10>; }; i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; Loading