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Commit f1c0f211 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Radhika Ranjan Soni
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ARM: dts: msm: add DT entries for LDO mode, byte and pixel clk for 8939 



Add DT entries for the MDSS DSI byte clock and pixel clock on
msm8939. This will enable the DSI drivers in successfully
registering the DSI byte and pixel clocks.

Also on msm8939, the DSI PHY regulator operates in LDO mode. Add
DT entries to enable LDO mode by default and program the DSI
registers with the corresponding LDO mode values.

Change-Id: I8baf0c300cb1d1a44c5e5866a6557793b8c5334a
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: default avatarRadhika Ranjan Soni <rrsoni@codeaurora.org>
parent 1559d923

arch/arm/boot/dts/qcom/msm8939-mdss.dtsi

+5 −2
Original line number Diff line number Diff line
@@ -119,12 +119,15 @@ 
		clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,

			 <&clock_gcc clk_gcc_mdss_ahb_clk>,

			 <&clock_gcc clk_gcc_mdss_axi_clk>,

			 <&clock_gcc_mdss clk_gcc_mdss_byte0_clk>,

			 <&clock_gcc_mdss clk_gcc_mdss_pclk0_clk>,

			 <&clock_gcc clk_gcc_mdss_esc0_clk>;

		clock-names = "mdp_core_clk", "iface_clk", "bus_clk",

				"core_clk";

				"byte_clk", "pixel_clk", "core_clk";

		qcom,regulator-ldo-mode;

		qcom,platform-strength-ctrl = [ff 06];

		qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];

		qcom,platform-regulator-settings = [07 09 03 00 20 00 01];

		qcom,platform-regulator-settings = [02 09 03 00 20 00 01];

		qcom,platform-lane-config = [00 00 00 00 00 00 00 01 97

			00 00 00 00 05 00 00 01 97

			00 00 00 00 0a 00 00 01 97