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Commit f18ce062 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add A304 GPU support for msmferrum"

parents 8db32049 52869f67

drivers/gpu/msm/a3xx_reg.h

+41 −40
Original line number Diff line number Diff line
@@ -546,53 +546,53 @@ 
#define A3XX_VBIF_PERF_PWR_CNT2_HI 0x307c



/* VBIF register offsets for A306 */

#define A306_VBIF_PERF_CNT_EN0 0x30c0

#define A306_VBIF_PERF_CNT_EN1 0x30c1

#define A306_VBIF_PERF_CNT_EN2 0x30c2

#define A306_VBIF_PERF_CNT_EN3 0x30c3

#define A306_VBIF_PERF_CNT_CLR0 0x30c8

#define A306_VBIF_PERF_CNT_CLR1 0x30c9

#define A306_VBIF_PERF_CNT_CLR2 0x30ca

#define A306_VBIF_PERF_CNT_CLR3 0x30cb

#define A306_VBIF_PERF_CNT_SEL0 0x30d0

#define A306_VBIF_PERF_CNT_SEL1 0x30d1

#define A306_VBIF_PERF_CNT_SEL2 0x30d2

#define A306_VBIF_PERF_CNT_SEL3 0x30d3

#define A306_VBIF_PERF_CNT_LOW0 0x30d8

#define A306_VBIF_PERF_CNT_LOW1 0x30d9

#define A306_VBIF_PERF_CNT_LOW2 0x30da

#define A306_VBIF_PERF_CNT_LOW3 0x30db

#define A306_VBIF_PERF_CNT_HIGH0 0x30e0

#define A306_VBIF_PERF_CNT_HIGH1 0x30e1

#define A306_VBIF_PERF_CNT_HIGH2 0x30e2

#define A306_VBIF_PERF_CNT_HIGH3 0x30e3



#define A306_VBIF_PERF_CNT_SEL_MASK 0x7F

#define A3XX_VBIF2_PERF_CNT_EN0 0x30c0

#define A3XX_VBIF2_PERF_CNT_EN1 0x30c1

#define A3XX_VBIF2_PERF_CNT_EN2 0x30c2

#define A3XX_VBIF2_PERF_CNT_EN3 0x30c3

#define A3XX_VBIF2_PERF_CNT_CLR0 0x30c8

#define A3XX_VBIF2_PERF_CNT_CLR1 0x30c9

#define A3XX_VBIF2_PERF_CNT_CLR2 0x30ca

#define A3XX_VBIF2_PERF_CNT_CLR3 0x30cb

#define A3XX_VBIF2_PERF_CNT_SEL0 0x30d0

#define A3XX_VBIF2_PERF_CNT_SEL1 0x30d1

#define A3XX_VBIF2_PERF_CNT_SEL2 0x30d2

#define A3XX_VBIF2_PERF_CNT_SEL3 0x30d3

#define A3XX_VBIF2_PERF_CNT_LOW0 0x30d8

#define A3XX_VBIF2_PERF_CNT_LOW1 0x30d9

#define A3XX_VBIF2_PERF_CNT_LOW2 0x30da

#define A3XX_VBIF2_PERF_CNT_LOW3 0x30db

#define A3XX_VBIF2_PERF_CNT_HIGH0 0x30e0

#define A3XX_VBIF2_PERF_CNT_HIGH1 0x30e1

#define A3XX_VBIF2_PERF_CNT_HIGH2 0x30e2

#define A3XX_VBIF2_PERF_CNT_HIGH3 0x30e3



#define A3XX_VBIF2_PERF_CNT_SEL_MASK 0x7F



/* offset of clear register from select register */

#define A306_VBIF_PERF_CLR_REG_SEL_OFF 8

#define A3XX_VBIF2_PERF_CLR_REG_SEL_OFF 8

/* offset of enable register from select register */

#define A306_VBIF_PERF_EN_REG_SEL_OFF 16

#define A3XX_VBIF2_PERF_EN_REG_SEL_OFF 16

/* offset of high counter from low counter value */

#define A306_VBIF_PERF_HIGH_REG_LOW_OFF 8



#define A306_VBIF_PERF_PWR_CNT_EN0 0x3100

#define A306_VBIF_PERF_PWR_CNT_EN1 0x3101

#define A306_VBIF_PERF_PWR_CNT_EN2 0x3102

#define A306_VBIF_PERF_PWR_CNT_CLR0 0x3108

#define A306_VBIF_PERF_PWR_CNT_CLR1 0x3109

#define A306_VBIF_PERF_PWR_CNT_CLR2 0x310A

#define A306_VBIF_PERF_PWR_CNT_LOW0 0x3110

#define A306_VBIF_PERF_PWR_CNT_LOW1 0x3111

#define A306_VBIF_PERF_PWR_CNT_LOW2 0x3112

#define A306_VBIF_PERF_PWR_CNT_HIGH0 0x3118

#define A306_VBIF_PERF_PWR_CNT_HIGH1 0x3119

#define A306_VBIF_PERF_PWR_CNT_HIGH2 0x311a

#define A3XX_VBIF2_PERF_HIGH_REG_LOW_OFF 8



#define A3XX_VBIF2_PERF_PWR_CNT_EN0 0x3100

#define A3XX_VBIF2_PERF_PWR_CNT_EN1 0x3101

#define A3XX_VBIF2_PERF_PWR_CNT_EN2 0x3102

#define A3XX_VBIF2_PERF_PWR_CNT_CLR0 0x3108

#define A3XX_VBIF2_PERF_PWR_CNT_CLR1 0x3109

#define A3XX_VBIF2_PERF_PWR_CNT_CLR2 0x310A

#define A3XX_VBIF2_PERF_PWR_CNT_LOW0 0x3110

#define A3XX_VBIF2_PERF_PWR_CNT_LOW1 0x3111

#define A3XX_VBIF2_PERF_PWR_CNT_LOW2 0x3112

#define A3XX_VBIF2_PERF_PWR_CNT_HIGH0 0x3118

#define A3XX_VBIF2_PERF_PWR_CNT_HIGH1 0x3119

#define A3XX_VBIF2_PERF_PWR_CNT_HIGH2 0x311a



/* offset of clear register from the enable register */

#define A306_VBIF_PERF_PWR_CLR_REG_EN_OFF 8

#define A3XX_VBIF2_PERF_PWR_CLR_REG_EN_OFF 8

/* offset of high counter from low counter value */

#define A306_VBIF_PERF_PWR_HIGH_REG_LOW_OFF 8

#define A3XX_VBIF2_PERF_PWR_HIGH_REG_LOW_OFF 8



#define A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL0 0x3800

#define A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL1 0x3801
@@ -869,6 +869,7 @@ 
#define RBBM_BLOCK_ID_MARB_3           0x2b



/* RBBM_CLOCK_CTL default value */

#define A304_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A305_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A305C_RBBM_CLOCK_CTL_DEFAULT  0xAAAAAAAA

#define A306_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

drivers/gpu/msm/adreno-gpulist.h

+11 −0
Original line number Diff line number Diff line
@@ -124,6 +124,17 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_128K,

	},

	{

		.gpurev = ADRENO_REV_A304,

		.core = 3,

		.major = 0,

		.minor = 4,

		.patchid = 0x00,

		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = (SZ_64K + SZ_32K),

	},

	{

		.gpurev = ADRENO_REV_A310,

		.core = 3,

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -130,6 +130,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A205 = 205,

	ADRENO_REV_A220 = 220,

	ADRENO_REV_A225 = 225,

	ADRENO_REV_A304 = 304,

	ADRENO_REV_A305 = 305,

	ADRENO_REV_A305C = 306,

	ADRENO_REV_A306 = 307,
@@ -750,6 +751,11 @@ static inline int adreno_is_a3xx(struct adreno_device *adreno_dev) 
		(ADRENO_GPUREV(adreno_dev) < 400));

}



static inline int adreno_is_a304(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A304);

}



static inline int adreno_is_a305(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A305);

drivers/gpu/msm/adreno_a3xx.c

+61 −42
Original line number Diff line number Diff line
@@ -177,7 +177,9 @@ const unsigned int a3xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = { 
unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device

							*adreno_dev)

{

	if (adreno_is_a305(adreno_dev))

	if (adreno_is_a304(adreno_dev))

		return A304_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a305(adreno_dev))

		return A305_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a305c(adreno_dev))

		return A305C_RBBM_CLOCK_CTL_DEFAULT;
@@ -810,7 +812,7 @@ static int a3xx_perfcounter_enable_pwr(struct adreno_device *adreno_dev, 
	return 0;

}



static int a306_perfcounter_enable_vbif(struct adreno_device *adreno_dev,

static int a3xx_perfcounter_enable_vbif2(struct adreno_device *adreno_dev,

					 unsigned int counter,

					 unsigned int countable)

{
@@ -821,22 +823,21 @@ static int a306_perfcounter_enable_vbif(struct adreno_device *adreno_dev, 
	if (counters == NULL)

		return -EINVAL;



	if (counter > 3 || countable > A306_VBIF_PERF_CNT_SEL_MASK)

	if (counter > 3 || countable > A3XX_VBIF2_PERF_CNT_SEL_MASK)

		return -EINVAL;



	reg = &counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs[counter];

	/* Write 1, followed by 0 to CLR register for clearing the counter */

	kgsl_regwrite(device, reg->select - A306_VBIF_PERF_CLR_REG_SEL_OFF, 1);

	kgsl_regwrite(device, reg->select - A306_VBIF_PERF_CLR_REG_SEL_OFF, 0);

	kgsl_regwrite(device, reg->select - A3XX_VBIF2_PERF_CLR_REG_SEL_OFF, 1);

	kgsl_regwrite(device, reg->select - A3XX_VBIF2_PERF_CLR_REG_SEL_OFF, 0);

	kgsl_regwrite(device, reg->select, countable);

	/* enable reg is 8 DWORDS before select reg */

	kgsl_regwrite(device, reg->select - A306_VBIF_PERF_EN_REG_SEL_OFF, 1);

	kgsl_regwrite(device, reg->select - A3XX_VBIF2_PERF_EN_REG_SEL_OFF, 1);

	counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs[counter].value = 0;

	return 0;



}





static int a3xx_perfcounter_enable_vbif(struct adreno_device *adreno_dev,

					 unsigned int counter,

					 unsigned int countable)
@@ -870,7 +871,7 @@ static int a3xx_perfcounter_enable_vbif(struct adreno_device *adreno_dev, 
	return 0;

}



static int a306_perfcounter_enable_vbif_pwr(struct adreno_device *adreno_dev,

static int a3xx_perfcounter_enable_vbif2_pwr(struct adreno_device *adreno_dev,

					     unsigned int counter)

{

	struct kgsl_device *device = &adreno_dev->dev;
@@ -882,9 +883,9 @@ static int a306_perfcounter_enable_vbif_pwr(struct adreno_device *adreno_dev, 


	reg = &counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF_PWR].regs[counter];

	/* Write 1, followed by 0 to CLR register for clearing the counter */

	kgsl_regwrite(device, reg->select + A306_VBIF_PERF_PWR_CLR_REG_EN_OFF,

	kgsl_regwrite(device, reg->select + A3XX_VBIF2_PERF_PWR_CLR_REG_EN_OFF,

			1);

	kgsl_regwrite(device, reg->select + A306_VBIF_PERF_PWR_CLR_REG_EN_OFF,

	kgsl_regwrite(device, reg->select + A3XX_VBIF2_PERF_PWR_CLR_REG_EN_OFF,

			0);

	kgsl_regwrite(device, reg->select, 1);

	counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF_PWR]
@@ -947,8 +948,10 @@ int a3xx_perfcounter_enable(struct adreno_device *adreno_dev, 
		if (adreno_is_a4xx(adreno_dev))

			return a4xx_perfcounter_enable_vbif(adreno_dev, counter,

								countable);

		else if (adreno_is_a306(adreno_dev))

			return a306_perfcounter_enable_vbif(adreno_dev, counter,

		else if (adreno_is_a306(adreno_dev) ||

			adreno_is_a304(adreno_dev))

			return a3xx_perfcounter_enable_vbif2(adreno_dev,

								counter,

								countable);

		else

			return a3xx_perfcounter_enable_vbif(adreno_dev, counter,
@@ -959,8 +962,9 @@ int a3xx_perfcounter_enable(struct adreno_device *adreno_dev, 
		if (adreno_is_a4xx(adreno_dev))

			return a4xx_perfcounter_enable_vbif_pwr(adreno_dev,

								counter);

		else if (adreno_is_a306(adreno_dev))

			return a306_perfcounter_enable_vbif_pwr(adreno_dev,

		else if (adreno_is_a306(adreno_dev) ||

			adreno_is_a304(adreno_dev))

			return a3xx_perfcounter_enable_vbif2_pwr(adreno_dev,

								counter);

		else

			return a3xx_perfcounter_enable_vbif_pwr(adreno_dev,
@@ -1057,7 +1061,7 @@ static uint64_t a3xx_perfcounter_read_pwr(struct adreno_device *adreno_dev, 
				.regs[counter].value;

}



static uint64_t a306_perfcounter_read_vbif(struct adreno_device *adreno_dev,

static uint64_t a3xx_perfcounter_read_vbif2(struct adreno_device *adreno_dev,

				unsigned int counter)

{

	struct kgsl_device *device = &adreno_dev->dev;
@@ -1071,12 +1075,12 @@ static uint64_t a306_perfcounter_read_vbif(struct adreno_device *adreno_dev, 
	reg = &counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs[counter];



	/* freeze counter */

	kgsl_regwrite(device, reg->select - A306_VBIF_PERF_EN_REG_SEL_OFF, 0);

	kgsl_regwrite(device, reg->select - A3XX_VBIF2_PERF_EN_REG_SEL_OFF, 0);

	kgsl_regread(device, reg->offset, &lo);

	kgsl_regread(device, reg->offset_hi, &hi);



	/* un-freeze counter */

	kgsl_regwrite(device, reg->select - A306_VBIF_PERF_EN_REG_SEL_OFF, 1);

	kgsl_regwrite(device, reg->select - A3XX_VBIF2_PERF_EN_REG_SEL_OFF, 1);



	return ((((uint64_t) hi) << 32) | lo)

		+ counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF]
@@ -1115,7 +1119,8 @@ static uint64_t a3xx_perfcounter_read_vbif(struct adreno_device *adreno_dev, 
				.regs[counter].value;

}



static uint64_t a306_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev,

static uint64_t

	a3xx_perfcounter_read_vbif2_pwr(struct adreno_device *adreno_dev,

				unsigned int counter)

{

	struct kgsl_device *device = &adreno_dev->dev;
@@ -1141,7 +1146,6 @@ static uint64_t a306_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev, 
			.regs[counter].value;

}





static uint64_t a3xx_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev,

				unsigned int counter)

{
@@ -1194,8 +1198,9 @@ uint64_t a3xx_perfcounter_read(struct adreno_device *adreno_dev, 
		if (adreno_is_a4xx(adreno_dev))

			return a4xx_perfcounter_read_vbif_pwr(adreno_dev,

								counter);

		else if (adreno_is_a306(adreno_dev))

			return a306_perfcounter_read_vbif_pwr(adreno_dev,

		else if (adreno_is_a306(adreno_dev) ||

			adreno_is_a304(adreno_dev))

			return a3xx_perfcounter_read_vbif2_pwr(adreno_dev,

								counter);

		else

			return a3xx_perfcounter_read_vbif_pwr(adreno_dev,
@@ -1206,8 +1211,9 @@ uint64_t a3xx_perfcounter_read(struct adreno_device *adreno_dev, 
		if (adreno_is_a4xx(adreno_dev))

			return a4xx_perfcounter_read_vbif(adreno_dev,

							counter);

		else if (adreno_is_a306(adreno_dev))

			return a306_perfcounter_read_vbif(adreno_dev,

		else if (adreno_is_a306(adreno_dev) ||

			adreno_is_a304(adreno_dev))

			return a3xx_perfcounter_read_vbif2(adreno_dev,

							counter);

		else

			return a3xx_perfcounter_read_vbif(adreno_dev,
@@ -1351,6 +1357,11 @@ void a3xx_busy_cycles(struct adreno_device *adreno_dev, 
}



/* VBIF registers start after 0x3000 so use 0x0 as end of list marker */

static const struct adreno_vbif_data a304_vbif[] = {

	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },

	{0, 0},

};



static const struct adreno_vbif_data a305_vbif[] = {

	/* Set up 16 deep read/write request queues */

	{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010 },
@@ -1490,6 +1501,7 @@ static const struct adreno_vbif_data a330v21_vbif[] = { 
};



static const struct adreno_vbif_platform a3xx_vbif_platforms[] = {

	{ adreno_is_a304, a304_vbif },

	{ adreno_is_a305, a305_vbif },

	{ adreno_is_a305c, a305c_vbif },

	{ adreno_is_a306, a306_vbif },
@@ -1663,27 +1675,33 @@ static struct adreno_perfcount_register a3xx_perfcounters_vbif_pwr[] = { 
	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT2_LO,

		A3XX_VBIF_PERF_PWR_CNT2_HI, -1, 0 },

};

static struct adreno_perfcount_register a306_perfcounters_vbif[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A306_VBIF_PERF_CNT_LOW0,

		A306_VBIF_PERF_CNT_HIGH0, -1, A306_VBIF_PERF_CNT_SEL0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A306_VBIF_PERF_CNT_LOW1,

		A306_VBIF_PERF_CNT_HIGH1, -1, A306_VBIF_PERF_CNT_SEL1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A306_VBIF_PERF_CNT_LOW2,

		A306_VBIF_PERF_CNT_HIGH2, -1, A306_VBIF_PERF_CNT_SEL2 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A306_VBIF_PERF_CNT_LOW3,

		A306_VBIF_PERF_CNT_HIGH3, -1, A306_VBIF_PERF_CNT_SEL3 },

static struct adreno_perfcount_register a3xx_perfcounters_vbif2[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW0,

		A3XX_VBIF2_PERF_CNT_HIGH0, -1, A3XX_VBIF2_PERF_CNT_SEL0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW1,

		A3XX_VBIF2_PERF_CNT_HIGH1, -1, A3XX_VBIF2_PERF_CNT_SEL1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW2,

		A3XX_VBIF2_PERF_CNT_HIGH2, -1, A3XX_VBIF2_PERF_CNT_SEL2 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW3,

		A3XX_VBIF2_PERF_CNT_HIGH3, -1, A3XX_VBIF2_PERF_CNT_SEL3 },

};

/*

 * Placing EN register in select field since vbif perf counters

 * dont have select register to program

 */

static struct adreno_perfcount_register a306_perfcounters_vbif_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A306_VBIF_PERF_PWR_CNT_LOW0,

		A306_VBIF_PERF_PWR_CNT_HIGH0, -1, A306_VBIF_PERF_PWR_CNT_EN0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A306_VBIF_PERF_PWR_CNT_LOW1,

		A306_VBIF_PERF_PWR_CNT_HIGH1, -1, A306_VBIF_PERF_PWR_CNT_EN1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A4XX_VBIF_PERF_PWR_CNT_LOW2,

		A306_VBIF_PERF_PWR_CNT_HIGH2, -1, A306_VBIF_PERF_PWR_CNT_EN2 },

static struct adreno_perfcount_register a3xx_perfcounters_vbif2_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0,

		0, A3XX_VBIF2_PERF_PWR_CNT_LOW0,

		A3XX_VBIF2_PERF_PWR_CNT_HIGH0, -1,

		A3XX_VBIF2_PERF_PWR_CNT_EN0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0,

		0, A3XX_VBIF2_PERF_PWR_CNT_LOW1,

		A3XX_VBIF2_PERF_PWR_CNT_HIGH1, -1,

		A3XX_VBIF2_PERF_PWR_CNT_EN1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0,

		0, A3XX_VBIF2_PERF_PWR_CNT_LOW2,

		A3XX_VBIF2_PERF_PWR_CNT_HIGH2, -1,

		A3XX_VBIF2_PERF_PWR_CNT_EN2 },

};



#define A3XX_PERFCOUNTER_GROUP(offset, name) \
@@ -1739,11 +1757,12 @@ int a3xx_perfcounter_init(struct adreno_device *adreno_dev) 
	if (adreno_is_a330(adreno_dev))

		a3xx_perfcounters_sp[3].countable = KGSL_PERFCOUNTER_BROKEN;



	if (adreno_is_a306(adreno_dev)) {

	if (adreno_is_a306(adreno_dev) ||

		adreno_is_a304(adreno_dev)) {

		counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs =

			a306_perfcounters_vbif;

			a3xx_perfcounters_vbif2;

		counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF_PWR].regs =

			a306_perfcounters_vbif_pwr;

			a3xx_perfcounters_vbif2_pwr;

	}



	return 0;

drivers/gpu/msm/adreno_ringbuffer.c

+2 −1
Original line number Diff line number Diff line
@@ -474,7 +474,8 @@ static void _ringbuffer_setup_common(struct adreno_ringbuffer *rb) 


	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	if (adreno_is_a305(adreno_dev) || adreno_is_a305c(adreno_dev) ||

		adreno_is_a306(adreno_dev) || adreno_is_a320(adreno_dev))

		adreno_is_a306(adreno_dev) || adreno_is_a320(adreno_dev) ||

		adreno_is_a304(adreno_dev))

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x000E0602);

	else if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev) ||

			adreno_is_a310(adreno_dev))