Loading drivers/power/qpnp-charger.c +25 −2 Original line number Diff line number Diff line Loading @@ -3123,6 +3123,17 @@ qpnp_chg_trim_ibat(struct qpnp_chg_chip *chip, u8 ibat_trim) IBAT_TRIM_HIGH_LIM)) return; } if (chip->type == SMBBP) { rc = qpnp_chg_masked_write(chip, chip->buck_base + SEC_ACCESS, 0xFF, 0xA5, 1); if (rc) { pr_err("failed to write SEC_ACCESS: %d\n", rc); return; } } ibat_trim |= IBAT_TRIM_GOOD_BIT; rc = qpnp_chg_write(chip, &ibat_trim, chip->buck_base + BUCK_CTRL_TRIM3, 1); Loading Loading @@ -3158,7 +3169,7 @@ qpnp_chg_input_current_settled(struct qpnp_chg_chip *chip) if (!chip->ibat_calibration_enabled) return 0; if (chip->type != SMBB) if (chip->type != SMBB && chip->type != SMBBP) return 0; rc = qpnp_chg_read(chip, ®, Loading @@ -3178,6 +3189,17 @@ qpnp_chg_input_current_settled(struct qpnp_chg_chip *chip) pr_debug("Improper ibat_trim value=%x setting to value=%x\n", ibat_trim, IBAT_TRIM_MEAN); ibat_trim = IBAT_TRIM_MEAN; if (chip->type == SMBBP) { rc = qpnp_chg_masked_write(chip, chip->buck_base + SEC_ACCESS, 0xFF, 0xA5, 1); if (rc) { pr_err("failed to write SEC_ACCESS: %d\n", rc); return rc; } } rc = qpnp_chg_masked_write(chip, chip->buck_base + BUCK_CTRL_TRIM3, IBAT_TRIM_OFFSET_MASK, ibat_trim, 1); Loading Loading @@ -5410,7 +5432,8 @@ qpnp_charger_probe(struct spmi_device *spmi) goto fail_chg_enable; } if (subtype == SMBB_BAT_IF_SUBTYPE) { if (subtype == SMBB_BAT_IF_SUBTYPE || subtype == SMBBP_BAT_IF_SUBTYPE) { chip->iadc_dev = qpnp_get_iadc(chip->dev, "chg"); if (IS_ERR(chip->iadc_dev)) { Loading Loading
drivers/power/qpnp-charger.c +25 −2 Original line number Diff line number Diff line Loading @@ -3123,6 +3123,17 @@ qpnp_chg_trim_ibat(struct qpnp_chg_chip *chip, u8 ibat_trim) IBAT_TRIM_HIGH_LIM)) return; } if (chip->type == SMBBP) { rc = qpnp_chg_masked_write(chip, chip->buck_base + SEC_ACCESS, 0xFF, 0xA5, 1); if (rc) { pr_err("failed to write SEC_ACCESS: %d\n", rc); return; } } ibat_trim |= IBAT_TRIM_GOOD_BIT; rc = qpnp_chg_write(chip, &ibat_trim, chip->buck_base + BUCK_CTRL_TRIM3, 1); Loading Loading @@ -3158,7 +3169,7 @@ qpnp_chg_input_current_settled(struct qpnp_chg_chip *chip) if (!chip->ibat_calibration_enabled) return 0; if (chip->type != SMBB) if (chip->type != SMBB && chip->type != SMBBP) return 0; rc = qpnp_chg_read(chip, ®, Loading @@ -3178,6 +3189,17 @@ qpnp_chg_input_current_settled(struct qpnp_chg_chip *chip) pr_debug("Improper ibat_trim value=%x setting to value=%x\n", ibat_trim, IBAT_TRIM_MEAN); ibat_trim = IBAT_TRIM_MEAN; if (chip->type == SMBBP) { rc = qpnp_chg_masked_write(chip, chip->buck_base + SEC_ACCESS, 0xFF, 0xA5, 1); if (rc) { pr_err("failed to write SEC_ACCESS: %d\n", rc); return rc; } } rc = qpnp_chg_masked_write(chip, chip->buck_base + BUCK_CTRL_TRIM3, IBAT_TRIM_OFFSET_MASK, ibat_trim, 1); Loading Loading @@ -5410,7 +5432,8 @@ qpnp_charger_probe(struct spmi_device *spmi) goto fail_chg_enable; } if (subtype == SMBB_BAT_IF_SUBTYPE) { if (subtype == SMBB_BAT_IF_SUBTYPE || subtype == SMBBP_BAT_IF_SUBTYPE) { chip->iadc_dev = qpnp_get_iadc(chip->dev, "chg"); if (IS_ERR(chip->iadc_dev)) { Loading