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Commit ef8777aa authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "power: smb135x-charger: Add interface to disable soft current compensation"

parents fce84756 c9d74e1a

Documentation/devicetree/bindings/power/smb135x-charger.txt

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ Optional Properties: 
					go in to unintentional reverse boost in such a situation and

					the float voltage compensation needs to be disabled to avoid

					that reverse boost.

- qcom,soft-current-comp-disabled	Set this property to disable charging current compensation

					if battery temperature exceeds soft JEITA thresholds.

- qcom,thermal-mitigation:		Array of input current limit values for different

					system thermal mitigation level.

- regulator-name			A string used as a descriptive name for OTG regulator.

drivers/platform/msm/qpnp-power-on.c

+2 −1
Original line number Diff line number Diff line
@@ -1591,7 +1591,6 @@ static int qpnp_pon_probe(struct spmi_device *spmi) 
		return rc;

	}



	boot_reason = ffs(pon_sts);



	index = ffs(pon_sts) - 1;

	cold_boot = !qpnp_pon_is_warm_reset();
@@ -1747,6 +1746,8 @@ static int qpnp_pon_probe(struct spmi_device *spmi) 
		list_add(&pon->list, &spon_dev_list);

		mutex_unlock(&spon_list_mutex);

		pon->is_spon = true;

	} else {

		boot_reason = ffs(pon_sts);

	}



	/* config whether store the hard reset reason */

drivers/power/qpnp-fg.c

+248 −142
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ module_param_named( 
);



static int fg_sense_type = -EINVAL;

static int fg_restart;



static int fg_est_dump;

module_param_named(
@@ -245,6 +246,11 @@ module_param_named( 
	battery_type, fg_batt_type, charp, S_IRUSR | S_IWUSR

);



static int fg_sram_update_period_ms = 30000;

module_param_named(

	sram_update_period_ms, fg_sram_update_period_ms, int, S_IRUSR | S_IWUSR

);



struct fg_irq {

	int			irq;

	unsigned long		disabled;
@@ -360,6 +366,7 @@ struct fg_chip { 
	struct power_supply	bms_psy;

	struct mutex		rw_lock;

	struct mutex		cyc_ctr_lock;

	struct mutex		sysfs_restart_lock;

	struct work_struct	batt_profile_init;

	struct work_struct	dump_sram;

	struct work_struct	status_change_work;
@@ -369,6 +376,7 @@ struct fg_chip { 
	struct work_struct	set_resume_soc_work;

	struct work_struct	rslow_comp_work;

	struct work_struct	init_work;

	struct work_struct	sysfs_restart_work;

	struct power_supply	*batt_psy;

	struct power_supply	*usb_psy;

	struct power_supply	*dc_psy;
@@ -1425,7 +1433,6 @@ static int64_t twos_compliment_extend(int64_t val, int nbytes) 
#define LSB_8B		9800

#define TEMP_LSB_16B	625

#define DECIKELVIN	2730

#define SRAM_PERIOD_UPDATE_MS		30000

#define SRAM_PERIOD_NO_ID_UPDATE_MS	100

#define FULL_PERCENT_28BIT		0xFFFFFFF

static void update_sram_data(struct fg_chip *chip, int *resched_ms)
@@ -1505,22 +1512,39 @@ static void update_sram_data(struct fg_chip *chip, int *resched_ms) 


	if (battid_valid) {

		complete_all(&chip->batt_id_avail);

		*resched_ms = SRAM_PERIOD_UPDATE_MS;

		*resched_ms = fg_sram_update_period_ms;

	} else {

		*resched_ms = SRAM_PERIOD_NO_ID_UPDATE_MS;

	}

	fg_relax(&chip->update_sram_wakeup_source);

}



#define SRAM_TIMEOUT_MS			3000

static void update_sram_data_work(struct work_struct *work)

{

	struct fg_chip *chip = container_of(work,

				struct fg_chip,

				update_sram_data.work);

	int resched_ms;

	int resched_ms, ret;

	bool tried_again = false;



wait:

	/* Wait for MEMIF access revoked */

	ret = wait_for_completion_interruptible_timeout(

			&chip->sram_access_revoked,

			msecs_to_jiffies(SRAM_TIMEOUT_MS));



	/* If we were interrupted wait again one more time. */

	if (ret == -ERESTARTSYS && !tried_again) {

		tried_again = true;

		goto wait;

	} else if (ret <= 0) {

		pr_err("transaction timed out ret=%d\n", ret);

		goto out;

	}

	update_sram_data(chip, &resched_ms);



out:

	schedule_delayed_work(

		&chip->update_sram_data,

		msecs_to_jiffies(resched_ms));
@@ -1544,7 +1568,6 @@ static void update_temp_data(struct work_struct *work) 


	fg_stay_awake(&chip->update_temp_wakeup_source);

	if (chip->sw_rbias_ctrl) {

		INIT_COMPLETION(chip->sram_access_revoked);

		rc = fg_mem_masked_write(chip, EXTERNAL_SENSE_SELECT,

				BATT_TEMP_CNTRL_MASK,

				BATT_TEMP_ON,
@@ -2731,6 +2754,7 @@ static irqreturn_t fg_mem_avail_irq_handler(int irq, void *_chip) 
		if ((fg_debug_mask & FG_IRQS)

				& (FG_MEM_DEBUG_READS | FG_MEM_DEBUG_WRITES))

			pr_info("sram access granted\n");

		INIT_COMPLETION(chip->sram_access_revoked);

		complete_all(&chip->sram_access_granted);

	} else {

		if ((fg_debug_mask & FG_IRQS)
@@ -3146,22 +3170,172 @@ static void update_cc_cv_setpoint(struct fg_chip *chip) 
			tmp[0], tmp[1], CC_CV_SETPOINT_REG);

}



#define V_PREDICTED_ADDR		0x540

#define V_CURRENT_PREDICTED_OFFSET	0

#define LOW_LATENCY			BIT(6)

#define PROFILE_LOAD_TIMEOUT_MS		5000

#define BATT_PROFILE_OFFSET		0x4C0

#define PROFILE_INTEGRITY_REG		0x53C

#define PROFILE_INTEGRITY_BIT		BIT(0)

#define FIRST_EST_DONE_BIT		BIT(5)

#define MAX_TRIES_FIRST_EST		3

#define FIRST_EST_WAIT_MS		2000

static int fg_do_restart(struct fg_chip *chip, bool write_profile)

{

	int rc;

	int tries = 0;

	u8 reg = 0;



	if (fg_debug_mask & FG_STATUS)

		pr_info("restarting fuel gauge...\n");

	/*

	 * release the sram access and configure the correct settings

	 * before re-requesting access.

	 */

	mutex_lock(&chip->rw_lock);

	fg_release_access(chip);



	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,

			NO_OTP_PROF_RELOAD, 0, 1);

	if (rc) {

		pr_err("failed to set no otp reload bit\n");

		goto unlock_and_fail;

	}



	/* unset the restart bits so the fg doesn't continuously restart */

	reg = REDO_FIRST_ESTIMATE | RESTART_GO;

	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,

			reg, 0, 1);

	if (rc) {

		pr_err("failed to unset fg restart: %d\n", rc);

		goto unlock_and_fail;

	}



	rc = fg_masked_write(chip, MEM_INTF_CFG(chip),

			LOW_LATENCY, LOW_LATENCY, 1);

	if (rc) {

		pr_err("failed to set low latency access bit\n");

		goto unlock_and_fail;

	}

	mutex_unlock(&chip->rw_lock);



	/* read once to get a fg cycle in */

	rc = fg_mem_read(chip, &reg, PROFILE_INTEGRITY_REG, 1, 0, 0);

	if (rc) {

		pr_err("failed to read profile integrity rc=%d\n", rc);

		goto fail;

	}



	/*

	 * If this is not the first time a profile has been loaded, sleep for

	 * 3 seconds to make sure the NO_OTP_RELOAD is cleared in memory

	 */

	if (chip->first_profile_loaded)

		msleep(3000);



	mutex_lock(&chip->rw_lock);

	fg_release_access(chip);

	rc = fg_masked_write(chip, MEM_INTF_CFG(chip), LOW_LATENCY, 0, 1);

	if (rc) {

		pr_err("failed to set low latency access bit\n");

		goto unlock_and_fail;

	}



	atomic_add_return(1, &chip->memif_user_cnt);

	mutex_unlock(&chip->rw_lock);



	if (write_profile) {

		/* write the battery profile */

		rc = fg_mem_write(chip, chip->batt_profile, BATT_PROFILE_OFFSET,

				chip->batt_profile_len, 0, 1);

		if (rc) {

			pr_err("failed to write profile rc=%d\n", rc);

			goto sub_and_fail;

		}

		/* write the integrity bits and release access */

		rc = fg_mem_masked_write(chip, PROFILE_INTEGRITY_REG,

				PROFILE_INTEGRITY_BIT,

				PROFILE_INTEGRITY_BIT, 0);

		if (rc) {

			pr_err("failed to write profile rc=%d\n", rc);

			goto sub_and_fail;

		}

	}



	/* decrement the user count so that memory access can be released */

	fg_release_access_if_necessary(chip);

	/*

	 * set the restart bits so that the next fg cycle will not reload

	 * the profile

	 */

	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,

			NO_OTP_PROF_RELOAD, NO_OTP_PROF_RELOAD, 1);

	if (rc) {

		pr_err("failed to set no otp reload bit\n");

		goto fail;

	}



	reg = REDO_FIRST_ESTIMATE | RESTART_GO;

	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,

			reg, reg, 1);

	if (rc) {

		pr_err("failed to set fg restart: %d\n", rc);

		goto fail;

	}



	/* wait for the first estimate to complete */

	for (tries = 0; tries < MAX_TRIES_FIRST_EST; tries++) {

		msleep(FIRST_EST_WAIT_MS);



		rc = fg_read(chip, &reg, INT_RT_STS(chip->soc_base), 1);

		if (rc) {

			pr_err("spmi read failed: addr=%03X, rc=%d\n",

					INT_RT_STS(chip->soc_base), rc);

		}

		if (reg & FIRST_EST_DONE_BIT)

			break;

		else

			if (fg_debug_mask & FG_STATUS)

				pr_info("waiting for est, tries = %d\n", tries);

	}

	if ((reg & FIRST_EST_DONE_BIT) == 0)

		pr_err("Battery profile reloading failed, no first estimate\n");



	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,

			NO_OTP_PROF_RELOAD, 0, 1);

	if (rc) {

		pr_err("failed to set no otp reload bit\n");

		goto fail;

	}

	/* unset the restart bits so the fg doesn't continuously restart */

	reg = REDO_FIRST_ESTIMATE | RESTART_GO;

	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,

			reg, 0, 1);

	if (rc) {

		pr_err("failed to unset fg restart: %d\n", rc);

		goto fail;

	}



	if (fg_debug_mask & FG_STATUS)

		pr_info("done!\n");

	return 0;



unlock_and_fail:

	mutex_unlock(&chip->rw_lock);

	goto fail;

sub_and_fail:

	fg_release_access_if_necessary(chip);

	goto fail;

fail:

	return -EINVAL;

}



#define V_PREDICTED_ADDR		0x540

#define V_CURRENT_PREDICTED_OFFSET	0

#define PROFILE_LOAD_TIMEOUT_MS		5000

#define FG_PROFILE_LEN			128

#define PROFILE_COMPARE_LEN		32

static int fg_batt_profile_init(struct fg_chip *chip)

{

	int rc = 0, ret;

	int len, tries;

	int len;

	struct device_node *node = chip->spmi->dev.of_node;

	struct device_node *batt_node, *profile_node;

	const char *data, *batt_type_str, *old_batt_type;
@@ -3325,131 +3499,12 @@ wait: 
				DUMP_PREFIX_NONE, 16, 1, chip->batt_profile,

				chip->batt_profile_len, false);



	/*

	 * release the sram access and configure the correct settings

	 * before re-requesting access.

	 */

	mutex_lock(&chip->rw_lock);

	fg_release_access(chip);



	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,

			NO_OTP_PROF_RELOAD, 0, 1);

	if (rc) {

		pr_err("failed to set no otp reload bit\n");

		goto unlock_and_fail;

	}



	/* unset the restart bits so the fg doesn't continuously restart */

	reg = REDO_FIRST_ESTIMATE | RESTART_GO;

	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,

			reg, 0, 1);

	if (rc) {

		pr_err("failed to unset fg restart: %d\n", rc);

		goto unlock_and_fail;

	}



	rc = fg_masked_write(chip, MEM_INTF_CFG(chip),

			LOW_LATENCY, LOW_LATENCY, 1);

	if (rc) {

		pr_err("failed to set low latency access bit\n");

		goto unlock_and_fail;

	}

	mutex_unlock(&chip->rw_lock);



	/* read once to get a fg cycle in */

	rc = fg_mem_read(chip, &reg, PROFILE_INTEGRITY_REG, 1, 0, 0);

	if (rc) {

		pr_err("failed to read profile integrity rc=%d\n", rc);

		goto fail;

	}



	/*

	 * If this is not the first time a profile has been loaded, sleep for

	 * 3 seconds to make sure the NO_OTP_RELOAD is cleared in memory

	 */

	if (chip->first_profile_loaded)

		msleep(3000);



	mutex_lock(&chip->rw_lock);

	fg_release_access(chip);

	rc = fg_masked_write(chip, MEM_INTF_CFG(chip), LOW_LATENCY, 0, 1);

	if (rc) {

		pr_err("failed to set low latency access bit\n");

		goto unlock_and_fail;

	}



	atomic_add_return(1, &chip->memif_user_cnt);

	mutex_unlock(&chip->rw_lock);



	/* write the battery profile */

	rc = fg_mem_write(chip, chip->batt_profile, BATT_PROFILE_OFFSET,

			chip->batt_profile_len, 0, 1);

	if (rc) {

		pr_err("failed to write profile rc=%d\n", rc);

		goto sub_and_fail;

	}



	/* write the integrity bits and release access */

	rc = fg_mem_masked_write(chip, PROFILE_INTEGRITY_REG,

			PROFILE_INTEGRITY_BIT, PROFILE_INTEGRITY_BIT, 0);

	rc = fg_do_restart(chip, true);

	if (rc) {

		pr_err("failed to write profile rc=%d\n", rc);

		goto sub_and_fail;

	}



	/* decrement the user count so that memory access can be released */

	fg_release_access_if_necessary(chip);

	/*

	 * set the restart bits so that the next fg cycle will reload

	 * the profile

	 */

	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,

			NO_OTP_PROF_RELOAD, NO_OTP_PROF_RELOAD, 1);

	if (rc) {

		pr_err("failed to set no otp reload bit\n");

		pr_err("restart failed: %d\n", rc);

		goto fail;

	}



	reg = REDO_FIRST_ESTIMATE | RESTART_GO;

	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,

			reg, reg, 1);

	if (rc) {

		pr_err("failed to set fg restart: %d\n", rc);

		goto fail;

	}



	/* wait for the first estimate to complete */

	for (tries = 0; tries < MAX_TRIES_FIRST_EST; tries++) {

		msleep(FIRST_EST_WAIT_MS);



		rc = fg_read(chip, &reg, INT_RT_STS(chip->soc_base), 1);

		if (rc) {

			pr_err("spmi read failed: addr=%03X, rc=%d\n",

					INT_RT_STS(chip->soc_base), rc);

		}

		if (reg & FIRST_EST_DONE_BIT)

			break;

		else

			if (fg_debug_mask & FG_STATUS)

				pr_info("waiting for est, tries = %d\n", tries);

	}

	if ((reg & FIRST_EST_DONE_BIT) == 0)

		pr_err("Battery profile reloading failed, no first estimate\n");



	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,

			NO_OTP_PROF_RELOAD, 0, 1);

	if (rc) {

		pr_err("failed to set no otp reload bit\n");

		goto fail;

	}

	/* unset the restart bits so the fg doesn't continuously restart */

	reg = REDO_FIRST_ESTIMATE | RESTART_GO;

	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,

			reg, 0, 1);

	if (rc) {

		pr_err("failed to unset fg restart: %d\n", rc);

		goto fail;

	}

done:

	if (fg_batt_type)

		chip->batt_type = fg_batt_type;
@@ -3471,12 +3526,6 @@ done: 
		power_supply_changed(&chip->bms_psy);

	fg_relax(&chip->profile_wakeup_source);

	return rc;

unlock_and_fail:

	mutex_unlock(&chip->rw_lock);

	goto fail;

sub_and_fail:

	fg_release_access_if_necessary(chip);

	goto fail;

fail:

	chip->batt_type = old_batt_type;

	if (chip->power_supply_registered)
@@ -3512,6 +3561,21 @@ static void batt_profile_init(struct work_struct *work) 
		pr_err("failed to initialize profile\n");

}



static void sysfs_restart_work(struct work_struct *work)

{

	struct fg_chip *chip = container_of(work,

				struct fg_chip,

				sysfs_restart_work);

	int rc;



	rc = fg_do_restart(chip, false);

	if (rc)

		pr_err("fg restart failed: %d\n", rc);

	mutex_lock(&chip->sysfs_restart_lock);

	fg_restart = 0;

	mutex_unlock(&chip->sysfs_restart_lock);

}



static void update_bcl_thresholds(struct fg_chip *chip)

{

	u8 data[4];
@@ -3924,9 +3988,13 @@ static void fg_cleanup(struct fg_chip *chip) 
	cancel_work_sync(&chip->cycle_count_work);

	cancel_work_sync(&chip->update_esr_work);

	cancel_work_sync(&chip->init_work);

	cancel_work_sync(&chip->sysfs_restart_work);

	power_supply_unregister(&chip->bms_psy);

	mutex_destroy(&chip->rslow_comp.lock);

	mutex_destroy(&chip->rw_lock);

	mutex_destroy(&chip->cyc_ctr_lock);

	mutex_destroy(&chip->learning_data.learning_lock);

	mutex_destroy(&chip->sysfs_restart_lock);

	wakeup_source_trash(&chip->resume_soc_wakeup_source.source);

	wakeup_source_trash(&chip->empty_check_wakeup_source.source);

	wakeup_source_trash(&chip->memif_wakeup_source.source);
@@ -4661,15 +4729,17 @@ static void delayed_init_work(struct work_struct *work) 
				init_work);



	/* hold memory access until initialization finishes */

	atomic_add_return(1, &chip->memif_user_cnt);

	fg_mem_lock(chip);



	rc = fg_hw_init(chip);

	if (rc) {

		pr_err("failed to hw init rc = %d\n", rc);

		fg_release_access_if_necessary(chip);

		fg_mem_release(chip);

		fg_cleanup(chip);

		return;

	}

	/* release memory access before update_sram_data is called */

	fg_mem_release(chip);



	schedule_delayed_work(

		&chip->update_jeita_setting,
@@ -4681,9 +4751,6 @@ static void delayed_init_work(struct work_struct *work) 
	if (chip->last_temp_update_time == 0)

		update_temp_data(&chip->update_temp_work.work);



	/* release memory access if necessary */

	fg_release_access_if_necessary(chip);



	if (!chip->use_otp_profile)

		schedule_work(&chip->batt_profile_init);
@@ -4734,6 +4801,7 @@ static int fg_probe(struct spmi_device *spmi) 
	mutex_init(&chip->cyc_ctr_lock);

	mutex_init(&chip->learning_data.learning_lock);

	mutex_init(&chip->rslow_comp.lock);

	mutex_init(&chip->sysfs_restart_lock);

	INIT_DELAYED_WORK(&chip->update_jeita_setting, update_jeita_setting);

	INIT_DELAYED_WORK(&chip->update_sram_data, update_sram_data_work);

	INIT_DELAYED_WORK(&chip->update_temp_work, update_temp_data);
@@ -4748,10 +4816,12 @@ static int fg_probe(struct spmi_device *spmi) 
	INIT_WORK(&chip->update_esr_work, update_esr_value);

	INIT_WORK(&chip->set_resume_soc_work, set_resume_soc_work);

	INIT_WORK(&chip->init_work, delayed_init_work);

	INIT_WORK(&chip->sysfs_restart_work, sysfs_restart_work);

	alarm_init(&chip->fg_cap_learning_alarm, ALARM_BOOTTIME,

			fg_cap_learning_alarm_cb);

	init_completion(&chip->sram_access_granted);

	init_completion(&chip->sram_access_revoked);

	complete_all(&chip->sram_access_revoked);

	init_completion(&chip->batt_id_avail);

	dev_set_drvdata(&spmi->dev, chip);
@@ -4898,11 +4968,13 @@ cancel_work: 
	cancel_work_sync(&chip->update_esr_work);

	cancel_work_sync(&chip->rslow_comp_work);

	cancel_work_sync(&chip->init_work);

	cancel_work_sync(&chip->sysfs_restart_work);

of_init_fail:

	mutex_destroy(&chip->rslow_comp.lock);

	mutex_destroy(&chip->rw_lock);

	mutex_destroy(&chip->cyc_ctr_lock);

	mutex_destroy(&chip->learning_data.learning_lock);

	mutex_destroy(&chip->sysfs_restart_lock);

	wakeup_source_trash(&chip->resume_soc_wakeup_source.source);

	wakeup_source_trash(&chip->empty_check_wakeup_source.source);

	wakeup_source_trash(&chip->memif_wakeup_source.source);
@@ -4930,7 +5002,7 @@ static void check_and_update_sram_data(struct fg_chip *chip) 
		&chip->update_temp_work, msecs_to_jiffies(time_left * 1000));



	next_update_time = chip->last_sram_update_time

		+ (SRAM_PERIOD_UPDATE_MS / 1000);

		+ (fg_sram_update_period_ms / 1000);



	if (next_update_time > current_time)

		time_left = next_update_time - current_time;
@@ -5010,6 +5082,40 @@ static struct kernel_param_ops fg_sense_type_ops = { 


module_param_cb(sense_type, &fg_sense_type_ops, &fg_sense_type, 0644);



static int fg_restart_set(const char *val, const struct kernel_param *kp)

{

	struct power_supply *bms_psy;

	struct fg_chip *chip;



	bms_psy = power_supply_get_by_name("bms");

	if (!bms_psy) {

		pr_err("bms psy not found\n");

		return 0;

	}

	chip = container_of(bms_psy, struct fg_chip, bms_psy);



	mutex_lock(&chip->sysfs_restart_lock);

	if (fg_restart != 0) {

		mutex_unlock(&chip->sysfs_restart_lock);

		return 0;

	}

	fg_restart = 1;

	mutex_unlock(&chip->sysfs_restart_lock);



	if (fg_debug_mask & FG_STATUS)

		pr_info("fuel gauge restart initiated from sysfs...\n");



	schedule_work(&chip->sysfs_restart_work);

	return 0;

}



static struct kernel_param_ops fg_restart_ops = {

	.set = fg_restart_set,

	.get = param_get_int,

};



module_param_cb(restart, &fg_restart_ops, &fg_restart, 0644);



static struct spmi_driver fg_driver = {

	.driver		= {

		.name	= QPNP_FG_DEV_NAME,

drivers/power/smb135x-charger.c

+17 −0
Original line number Diff line number Diff line
@@ -111,6 +111,8 @@ 
#define CFG_1A_REG			0x1A

#define HOT_SOFT_VFLOAT_COMP_EN_BIT	BIT(3)

#define COLD_SOFT_VFLOAT_COMP_EN_BIT	BIT(2)

#define HOT_SOFT_CURRENT_COMP_EN_BIT	BIT(1)

#define COLD_SOFT_CURRENT_COMP_EN_BIT	BIT(0)



#define VFLOAT_REG			0x1E
@@ -382,6 +384,7 @@ struct smb135x_chg { 
	int				skip_reads;

	u32				workaround_flags;

	bool				soft_vfloat_comp_disabled;

	bool				soft_current_comp_disabled;

	struct mutex			irq_complete;

	struct regulator		*therm_bias_vreg;

	struct regulator		*usb_pullup_vreg;
@@ -3642,6 +3645,17 @@ static int smb135x_hw_init(struct smb135x_chg *chip) 
		}

	}



	if (chip->soft_current_comp_disabled) {

		mask = HOT_SOFT_CURRENT_COMP_EN_BIT

				| COLD_SOFT_CURRENT_COMP_EN_BIT;

		rc = smb135x_masked_write(chip, CFG_1A_REG, mask, 0);

		if (rc < 0) {

			dev_err(chip->dev, "Couldn't disable soft current rc = %d\n",

					rc);

			goto free_regulator;

		}

	}



	/*

	 * Command mode for OTG control. This gives us RID interrupts but keeps

	 * enabling the 5V OTG via i2c register control
@@ -3775,6 +3789,9 @@ static int smb_parse_dt(struct smb135x_chg *chip) 
	chip->soft_vfloat_comp_disabled = of_property_read_bool(node,

					"qcom,soft-vfloat-comp-disabled");



	chip->soft_current_comp_disabled = of_property_read_bool(node,

					"qcom,soft-current-comp-disabled");



	if (of_find_property(node, "therm-bias-supply", NULL)) {

		/* get the thermistor bias regulator */

		chip->therm_bias_vreg = devm_regulator_get(chip->dev,