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Commit ef54a8bd authored by Rohit Vaswani's avatar Rohit Vaswani
Browse files

soc: cpu_pwr_ctl: Change the CPU power up sequence for 8994 



MSM8994 observed some droops with the bypass LDO setup.
Remove this from the sequence and change the delay between the
writes to be 1 micro-second.

Change-Id: Ied4199ecdbbd84a33d227f5678a88af8c2c6fca7
Signed-off-by: default avatarRohit Vaswani <rvaswani@codeaurora.org>
parent 1dc0defc

drivers/soc/qcom/cpu_pwr_ctl.c

+4 −9
Original line number Diff line number Diff line
@@ -291,20 +291,15 @@ int msm8994_unclamp_secondary_arm_cpu(unsigned int cpu) 
		goto out_acc_reg;

	}



	/* Bypass LDO */

	writel_relaxed(0x00000001, ldo_bhs_reg + LDO_BHS_PWR_CTL);

	mb();

	udelay(2);



	/* Assert head switch enable few */

	writel_relaxed(0x00000001, acc_reg + CPU_PWR_GATE_CTL);

	mb();

	udelay(2);

	udelay(1);



	/* Assert head switch enable rest */

	writel_relaxed(0x00000003, acc_reg + CPU_PWR_GATE_CTL);

	mb();

	udelay(2);

	udelay(1);



	/* De-assert coremem clamp. This is asserted by default */

	writel_relaxed(0x00000079, acc_reg + CPU_PWR_CTL);
@@ -313,7 +308,7 @@ int msm8994_unclamp_secondary_arm_cpu(unsigned int cpu) 
	/* Close coremem array gdhs */

	writel_relaxed(0x0000007D, acc_reg + CPU_PWR_CTL);

	mb();

	udelay(2);

	udelay(1);



	/* De-assert clamp */

	writel_relaxed(0x0000003D, acc_reg + CPU_PWR_CTL);
@@ -322,7 +317,7 @@ int msm8994_unclamp_secondary_arm_cpu(unsigned int cpu) 
	/* De-assert clamp */

	writel_relaxed(0x0000003C, acc_reg + CPU_PWR_CTL);

	mb();

	udelay(2);

	udelay(1);



	/* De-assert core0 reset */

	writel_relaxed(0x0000000C, acc_reg + CPU_PWR_CTL);