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Commit ee51889d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: mdss: add PLL clock support for 20nm HDMI PHY"

parents 4f45396f d01bb071

Documentation/devicetree/bindings/fb/mdss-pll.txt

+2 −1
Original line number Diff line number Diff line
@@ -8,7 +8,8 @@ Required properties: 
- compatible:		Compatible name used in the driver. Should be one of:

			"qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939",

			"qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994",

			"qcom,mdss_dsi_pll_8994", "qcom,mdss_hdmi_pll"

			"qcom,mdss_dsi_pll_8994", "qcom,mdss_hdmi_pll",

			"qcom,mdss_hdmi_pll_8994"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

drivers/clk/qcom/mdss/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -6,3 +6,4 @@ obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28lpm.o 
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-20nm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o

drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c

0 → 100644
+1247 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/qcom/mdss/mdss-hdmi-pll.h

+2 −0
Original line number Diff line number Diff line
@@ -26,4 +26,6 @@ struct hdmi_pll_vco_clk { 
int hdmi_pll_clock_register(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);



int hdmi_20nm_pll_clock_register(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);

#endif

drivers/clk/qcom/mdss/mdss-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -143,6 +143,8 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, 
		pll_res->pll_interface_type = MDSS_EDP_PLL;

	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) {

		pll_res->pll_interface_type = MDSS_HDMI_PLL;

	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8994")) {

		pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;

	} else {

		goto err;

	}
@@ -180,6 +182,8 @@ static int mdss_pll_clock_register(struct platform_device *pdev, 
		break;

	case MDSS_HDMI_PLL:

		rc = hdmi_pll_clock_register(pdev, pll_res);

	case MDSS_HDMI_PLL_20NM:

		rc = hdmi_20nm_pll_clock_register(pdev, pll_res);

		break;

	case MDSS_UNKNOWN_PLL:

	default:
@@ -314,6 +318,7 @@ static int mdss_pll_remove(struct platform_device *pdev) 
static const struct of_device_id mdss_pll_dt_match[] = {

	{.compatible = "qcom,mdss_dsi_pll_8974"},

	{.compatible = "qcom,mdss_dsi_pll_8994"},

	{.compatible = "qcom,mdss_hdmi_pll_8994"},

	{.compatible = "qcom,mdss_dsi_pll_8916"},

	{.compatible = "qcom,mdss_dsi_pll_8939"},

	{.compatible = "qcom,mdss_edp_pll"},