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Commit ee41a6ea authored by Vignesh Radhakrishnan's avatar Vignesh Radhakrishnan
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ARM: dts: msm add coresight byte counter interrupt for 8092 



The CoreSight block can produce an interrupt on transfer of
programmed number of bytes to ETR-memory. Add device tree
entry to support this feature.

Change-Id: Ia1c3a045b78380e3f739af590e5329a12c9552e2
Signed-off-by: default avatarVignesh Radhakrishnan <vigneshr@codeaurora.org>
parent a9413d4c

arch/arm/boot/dts/mpq8092-coresight.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
		reg = <0xfc326000 0x1000>,

		      <0xfc37c000 0x3000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 270 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;