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Commit edf2b81b authored by Prabhat Awasthi's avatar Prabhat Awasthi
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ARM: dts: msm: Add GPU properties for msmferrum



Add device specific GPU properties for msmferrum.

Change-Id: I58425bded01edcdd0af0d8d5acc99307936ca4c8
Signed-off-by: default avatarPrabhat Awasthi <pawasthi@codeaurora.org>
parent 9f25a3ef
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	msm_gpu: qcom,kgsl-3d0@01c00000 {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		reg = <0x01c00000 0x10000
		       0x01c10000 0x10000>;
		reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
		interrupts = <0 33 0>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;

		qcom,chipid = <0x03000400>;

		qcom,initial-pwrlevel = <1>;

		/* Idle Timeout = HZ/12 */
		qcom,idle-timeout = <8>;
		qcom,strtstp-sleepwake;

		/*
		 * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM |
		 * KGSL_CLK_MEM_IFACE | KGSL_CLK_ALT_MEM_IFACE
		 */
		qcom,clk-map = <0x0000005E>;
		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,
			<&clock_gcc clk_gcc_oxili_ahb_clk>,
			<&clock_gcc clk_gcc_oxili_gmem_clk>,
			<&clock_gcc clk_gcc_bimc_gfx_clk>,
			<&clock_gcc clk_gcc_bimc_gpu_clk>,
			<&clock_gcc clk_gcc_gtcu_ahb_clk>;
		clock-names = "core_clk", "iface_clk", "mem_clk",
				"mem_iface_clk", "alt_mem_iface_clk",
				"gtcu_iface_clk";

		/* Bus Scale Settings */
		qcom,msm-bus,name = "grp3d";
		qcom,msm-bus,num-cases = <4>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<26 512 0 0>,
			<26 512 0 1600000>,
			<26 512 0 3200000>,
			<26 512 0 4264000>;

		/* GDSC oxili regulators */
		vdd-supply = <&gdsc_oxili_gx>;

		/* IOMMU Data */
		iommu = <&gfx_iommu>;

		/* CPU latency parameter */
		qcom,pm-qos-latency = <701>;

		/* Power levels */
		qcom,gpu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <400000000>;
				qcom,bus-freq = <3>;
			};

			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <307200000>;
				qcom,bus-freq = <2>;
			};

			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <200000000>;
				qcom,bus-freq = <1>;
			};

			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <19200000>;
				qcom,bus-freq = <0>;
			};
		};

	};
};
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@@ -116,6 +116,7 @@
#include "msmferrum-ipcrouter.dtsi"
#include "msm-gdsc-8916.dtsi"
#include "msmferrum-iommu.dtsi"
#include "msmferrum-gpu.dtsi"

&soc {
	#address-cells = <1>;