Loading arch/arm/boot/dts/qcom/msm8992-pinctrl.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -199,6 +199,23 @@ }; }; pmx_i2c_2 { qcom,pins = <&gp 6>, <&gp 7>; /* SDA, SCL */ qcom,num-grp-pins = <2>; qcom,pin-func = <3>; label = "pmx_i2c_2"; i2c_2_active: i2c_2_active { drive-strength = <2>; bias-disable; }; i2c_2_sleep: i2c_2_sleep { drive-strength = <2>; bias-disable; }; }; eth-irq { qcom,pins = <&gp 75>; qcom,num-grp-pins = <1>; Loading arch/arm/boot/dts/qcom/msm8992.dtsi +26 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ spi0 = &spi_0; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD card slot */ i2c2 = &i2c_2; }; cpus { Loading Loading @@ -335,6 +336,31 @@ qcom,master-id = <86>; }; i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0xf9924000 0x1000>, <0xf9904000 0x19000>; interrupt-names = "qup_irq", "bam_irq"; interrupts = <0 96 0>, <0 238 0>; qcom,clk-freq-out = <100000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_2_active>; pinctrl-1 = <&i2c_2_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,bam-pipe-idx-cons = <14>; qcom,bam-pipe-idx-prod = <15>; qcom,master-id = <86>; }; sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; Loading Loading
arch/arm/boot/dts/qcom/msm8992-pinctrl.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -199,6 +199,23 @@ }; }; pmx_i2c_2 { qcom,pins = <&gp 6>, <&gp 7>; /* SDA, SCL */ qcom,num-grp-pins = <2>; qcom,pin-func = <3>; label = "pmx_i2c_2"; i2c_2_active: i2c_2_active { drive-strength = <2>; bias-disable; }; i2c_2_sleep: i2c_2_sleep { drive-strength = <2>; bias-disable; }; }; eth-irq { qcom,pins = <&gp 75>; qcom,num-grp-pins = <1>; Loading
arch/arm/boot/dts/qcom/msm8992.dtsi +26 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ spi0 = &spi_0; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD card slot */ i2c2 = &i2c_2; }; cpus { Loading Loading @@ -335,6 +336,31 @@ qcom,master-id = <86>; }; i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0xf9924000 0x1000>, <0xf9904000 0x19000>; interrupt-names = "qup_irq", "bam_irq"; interrupts = <0 96 0>, <0 238 0>; qcom,clk-freq-out = <100000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_2_active>; pinctrl-1 = <&i2c_2_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,bam-pipe-idx-cons = <14>; qcom,bam-pipe-idx-prod = <15>; qcom,master-id = <86>; }; sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; Loading