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Commit ea57b5d6 authored by Vignesh Radhakrishnan's avatar Vignesh Radhakrishnan
Browse files

ARM: dts: msm: add etm devices for remote procs on 8092 



Add ETM devices for remote processors to support ETM tracing on
these processors.

change-Id: Ie5ef74816e493224b4908e0755428348dabc12e1
Signed-off-by: default avatarVignesh Radhakrishnan <vigneshr@codeaurora.org>
parent 2004ed27

arch/arm/boot/dts/mpq8092-coresight.dtsi

+42 −20
Original line number Diff line number Diff line
@@ -218,12 +218,34 @@ 
		qcom,round-robin;

	};



	audio_etm0 {

		compatible = "qcom,coresight-audio-etm";



		coresight-id = <14>;

		coresight-name = "coresight-audio-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <2>;

	};



	rpm_etm0 {

		compatible = "qcom,coresight-rpm-etm";



		coresight-id = <15>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <0>;

	};



	csr: csr@fc301000 {

		compatible = "qcom,coresight-csr";

		reg = <0xfc301000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <14>;

		coresight-id = <16>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;
@@ -235,7 +257,7 @@ 
		reg = <0xfc310000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-id = <17>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;

	};
@@ -245,7 +267,7 @@ 
		reg = <0xfc311000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-id = <18>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;

	};
@@ -255,7 +277,7 @@ 
		reg = <0xfc312000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <17>;

		coresight-id = <19>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;

	};
@@ -265,7 +287,7 @@ 
		reg = <0xfc313000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <18>;

		coresight-id = <20>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;

	};
@@ -275,7 +297,7 @@ 
		reg = <0xfc314000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <19>;

		coresight-id = <21>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;

	};
@@ -285,7 +307,7 @@ 
		reg = <0xfc315000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <20>;

		coresight-id = <22>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;

	};
@@ -295,7 +317,7 @@ 
		reg = <0xfc316000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <21>;

		coresight-id = <23>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;

	};
@@ -305,7 +327,7 @@ 
		reg = <0xfc317000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <22>;

		coresight-id = <24>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;

	};
@@ -315,7 +337,7 @@ 
		reg = <0xfc318000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <23>;

		coresight-id = <25>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;

	};
@@ -325,7 +347,7 @@ 
		reg = <0xfc350000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <24>;

		coresight-id = <26>;

		coresight-name = "coresight-cti-l2";

		coresight-nr-inports = <0>;

	};
@@ -335,7 +357,7 @@ 
		reg = <0xfc351000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-id = <27>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

	};
@@ -345,7 +367,7 @@ 
		reg = <0xfc352000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <26>;

		coresight-id = <28>;

		coresight-name = "coresight-cti-cpu1";

		coresight-nr-inports = <0>;

	};
@@ -355,7 +377,7 @@ 
		reg = <0xfc353000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <27>;

		coresight-id = <29>;

		coresight-name = "coresight-cti-cpu2";

		coresight-nr-inports = <0>;

	};
@@ -365,7 +387,7 @@ 
		reg = <0xfc354000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <28>;

		coresight-id = <30>;

		coresight-name = "coresight-cti-cpu3";

		coresight-nr-inports = <0>;

	};
@@ -375,7 +397,7 @@ 
		reg = <0xfc330000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <29>;

		coresight-id = <31>;

		coresight-name = "coresight-cti-video-cpu0";

		coresight-nr-inports = <0>;

	};
@@ -385,7 +407,7 @@ 
		reg = <0xfc33c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <30>;

		coresight-id = <32>;

		coresight-name = "coresight-cti-audio-cpu0";

		coresight-nr-inports = <0>;

	};
@@ -395,7 +417,7 @@ 
		reg = <0xfc360000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <31>;

		coresight-id = <33>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;

	};
@@ -405,7 +427,7 @@ 
		reg = <0xfc36b000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <32>;

		coresight-id = <34>;

		coresight-name = "coresight-cti-vpu-cpu0";

		coresight-nr-inports = <0>;

	};
@@ -419,7 +441,7 @@ 
			<0xfc747060 0x80>;

		reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux",

			    "bcss-mux";

		coresight-id = <33>;

		coresight-id = <35>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;