Loading arch/arm/boot/dts/qcom/msmtellurium-rumi.dts +6 −0 Original line number Diff line number Diff line Loading @@ -26,3 +26,9 @@ clock-frequency = <10000000>; }; }; &blsp1_uart2 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; }; arch/arm/boot/dts/qcom/msmtellurium-sim.dts +6 −0 Original line number Diff line number Diff line Loading @@ -20,3 +20,9 @@ compatible = "qcom,msmtellurium-sim", "qcom,msmtellurium", "qcom,sim"; qcom,board-id= <16 0>; }; &blsp1_uart2 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; }; arch/arm/boot/dts/qcom/msmtellurium.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -389,4 +389,14 @@ qcom,smdpkt-dev-name = "smd_pkt_loopback"; }; }; blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; }; Loading
arch/arm/boot/dts/qcom/msmtellurium-rumi.dts +6 −0 Original line number Diff line number Diff line Loading @@ -26,3 +26,9 @@ clock-frequency = <10000000>; }; }; &blsp1_uart2 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; };
arch/arm/boot/dts/qcom/msmtellurium-sim.dts +6 −0 Original line number Diff line number Diff line Loading @@ -20,3 +20,9 @@ compatible = "qcom,msmtellurium-sim", "qcom,msmtellurium", "qcom,sim"; qcom,board-id= <16 0>; }; &blsp1_uart2 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; };
arch/arm/boot/dts/qcom/msmtellurium.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -389,4 +389,14 @@ qcom,smdpkt-dev-name = "smd_pkt_loopback"; }; }; blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; };