Loading drivers/video/msm/mdss/mdss_dsi.h +3 −0 Original line number Diff line number Diff line Loading @@ -176,6 +176,9 @@ enum dsi_pm_type { #define DSI_BTA_TERM BIT(1) #define DSI_CMD_TERM BIT(0) #define DSI_DATA_LANES_STOP_STATE 0xF #define DSI_CLK_LANE_STOP_STATE BIT(4) /* offsets for dynamic refresh */ #define DSI_DYNAMIC_REFRESH_CTRL 0x200 #define DSI_DYNAMIC_REFRESH_PIPE_DELAY 0x204 Loading drivers/video/msm/mdss/mdss_dsi_host.c +22 −7 Original line number Diff line number Diff line Loading @@ -1942,7 +1942,7 @@ static int dsi_event_thread(void *data) struct mdss_dsi_ctrl_pdata *ctrl; unsigned long flag; struct sched_param param; u32 todo = 0; u32 todo = 0, ln_status; int ret; param.sched_priority = 16; Loading Loading @@ -1991,13 +1991,28 @@ static int dsi_event_thread(void *data) mdss_dsi_sw_reset(ctrl, true); if (todo & DSI_EV_DLNx_FIFO_OVERFLOW) { pr_debug("%s: Handling overflow event\n", __func__); mutex_lock(&dsi_mtx); /* * Run the overflow recovery sequence only when * data lanes are in stop state and * clock lane is not in Stop State. */ ln_status = MIPI_INP(ctrl->ctrl_base + 0x00a8); pr_debug("%s: lane_status: 0x%x\n", __func__, ln_status); if (ctrl->recovery && (ln_status & DSI_DATA_LANES_STOP_STATE) && !(ln_status & DSI_CLK_LANE_STOP_STATE)) { pr_debug("%s: Handling overflow event.\n", __func__); mdss_dsi_clk_ctrl(ctrl, DSI_ALL_CLKS, 1); mdss_dsi_ctl_phy_reset(ctrl); mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 1); mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 1); mdss_dsi_clk_ctrl(ctrl, DSI_ALL_CLKS, 0); } mutex_unlock(&dsi_mtx); } Loading Loading
drivers/video/msm/mdss/mdss_dsi.h +3 −0 Original line number Diff line number Diff line Loading @@ -176,6 +176,9 @@ enum dsi_pm_type { #define DSI_BTA_TERM BIT(1) #define DSI_CMD_TERM BIT(0) #define DSI_DATA_LANES_STOP_STATE 0xF #define DSI_CLK_LANE_STOP_STATE BIT(4) /* offsets for dynamic refresh */ #define DSI_DYNAMIC_REFRESH_CTRL 0x200 #define DSI_DYNAMIC_REFRESH_PIPE_DELAY 0x204 Loading
drivers/video/msm/mdss/mdss_dsi_host.c +22 −7 Original line number Diff line number Diff line Loading @@ -1942,7 +1942,7 @@ static int dsi_event_thread(void *data) struct mdss_dsi_ctrl_pdata *ctrl; unsigned long flag; struct sched_param param; u32 todo = 0; u32 todo = 0, ln_status; int ret; param.sched_priority = 16; Loading Loading @@ -1991,13 +1991,28 @@ static int dsi_event_thread(void *data) mdss_dsi_sw_reset(ctrl, true); if (todo & DSI_EV_DLNx_FIFO_OVERFLOW) { pr_debug("%s: Handling overflow event\n", __func__); mutex_lock(&dsi_mtx); /* * Run the overflow recovery sequence only when * data lanes are in stop state and * clock lane is not in Stop State. */ ln_status = MIPI_INP(ctrl->ctrl_base + 0x00a8); pr_debug("%s: lane_status: 0x%x\n", __func__, ln_status); if (ctrl->recovery && (ln_status & DSI_DATA_LANES_STOP_STATE) && !(ln_status & DSI_CLK_LANE_STOP_STATE)) { pr_debug("%s: Handling overflow event.\n", __func__); mdss_dsi_clk_ctrl(ctrl, DSI_ALL_CLKS, 1); mdss_dsi_ctl_phy_reset(ctrl); mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 1); mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 1); mdss_dsi_clk_ctrl(ctrl, DSI_ALL_CLKS, 0); } mutex_unlock(&dsi_mtx); } Loading