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Commit e973d54b authored by Tarun Karra's avatar Tarun Karra Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Idle GPU after IOMMU V1 TLB flush 



After TLB flush on IOMMU V1, stall prefetch parser until
GPU is idle, this guarantees GPU is completely idle
after executing TLB flush instructions. This prevents
prefetching GPU instructions which could trigger hardware
page table walk while TLB flush instructions are
still being executed by GPU.

CRs-Fixed: 541950
Change-Id: Iaf5e577beb640bc42b9a1e29c96d06b125629860
Signed-off-by: default avatarTarun Karra <tkarra@codeaurora.org>
parent cb167fec

drivers/gpu/msm/adreno.c

+8 −0
Original line number Diff line number Diff line
@@ -806,6 +806,8 @@ static unsigned int _adreno_iommu_setstate_v1(struct kgsl_device *device, 
	int i;

	unsigned int ttbr0, tlbiall, tlbstatus, tlbsync, mmu_ctrl;



	cmds += adreno_add_idle_cmds(adreno_dev, cmds);



	for (i = 0; i < num_iommu_units; i++) {

		ttbr0_val = kgsl_mmu_get_default_ttbr0(&device->mmu,

				i, KGSL_IOMMU_CONTEXT_USER);
@@ -912,8 +914,14 @@ static unsigned int _adreno_iommu_setstate_v1(struct kgsl_device *device, 
			else

				cmds += adreno_wait_reg_eq(cmds, tlbstatus, 0,

					KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE, 0xF);

			/* release all commands with wait_for_me */

			*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);

			*cmds++ = 0;

		}

	}



	cmds += adreno_add_idle_cmds(adreno_dev, cmds);



	return cmds - cmds_orig;

}

drivers/gpu/msm/adreno.h

+1 −3
Original line number Diff line number Diff line
@@ -756,9 +756,7 @@ static inline int adreno_add_idle_cmds(struct adreno_device *adreno_dev, 
	*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);

	*cmds++ = 0;



	if ((adreno_dev->gpurev == ADRENO_REV_A305) ||

		(adreno_dev->gpurev == ADRENO_REV_A305C) ||

		(adreno_dev->gpurev == ADRENO_REV_A320)) {

	if (adreno_is_a3xx(adreno_dev)) {

		*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);

		*cmds++ = 0;

	}