Loading arch/arm/boot/dts/qcom/msm8992.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -1184,6 +1184,22 @@ qcom,master-id = <86>; }; dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9904000 0x19000>; interrupts = <0 238 0>; qcom,summing-threshold = <10>; }; dma_blsp2: qcom,sps-dma@f9944000 { /* BLSP2 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9944000 0x19000>; interrupts = <0 239 0>; qcom,summing-threshold = <10>; }; tspp: msm_tspp@f99d8000 { compatible = "qcom,msm_tspp"; reg = <0xf99d8000 0x1000>, /* MSM_TSIF0_PHYS */ Loading Loading
arch/arm/boot/dts/qcom/msm8992.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -1184,6 +1184,22 @@ qcom,master-id = <86>; }; dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9904000 0x19000>; interrupts = <0 238 0>; qcom,summing-threshold = <10>; }; dma_blsp2: qcom,sps-dma@f9944000 { /* BLSP2 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0xf9944000 0x19000>; interrupts = <0 239 0>; qcom,summing-threshold = <10>; }; tspp: msm_tspp@f99d8000 { compatible = "qcom,msm_tspp"; reg = <0xf99d8000 0x1000>, /* MSM_TSIF0_PHYS */ Loading