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Commit e9340749 authored by Vijayavardhan Vennapusa's avatar Vijayavardhan Vennapusa
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USB: dwc3-msm: Add support for 24MHz utmi clock 



For ref clk based SOF/ITP generation, utmi clock needs to be set
to frequencies like 19.2MHz, 24MHz etc. Hence add support for
setting utmi clock to 24MHz.

Change-Id: Ia64eaa5320846ab219c516f43e6dcdf0fb05eb89
Signed-off-by: default avatarVijayavardhan Vennapusa <vvreddy@codeaurora.org>
parent 90f1b5b9

Documentation/devicetree/bindings/usb/msm-ssusb.txt

+1 −1
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ Optional properties : 
  passed to secure channel manager(scm) driver. scm driver uses this device

  id to restore USB controller related security configuration after coming

  out of the controller power collapse.

- qcom,ref-clk-rate: Indicates refclk frequency (in Hz) to the core. If not

- qcom,utmi-clk-rate: Indicates refclk frequency (in Hz) to the core. If not

  specified, default of 19.2MHz is assumed.

- qcom,reset_hsphy_sleep_clk_on_init: If present, the HSUSB PHY sleep clock is

  being reset in initialization.

drivers/usb/dwc3/dwc3-msm.c

+30 −10
Original line number Diff line number Diff line
@@ -135,7 +135,8 @@ struct dwc3_msm { 
	struct clk		*sleep_clk;

	struct clk		*hsphy_sleep_clk;

	struct clk		*utmi_clk;

	unsigned long		ref_clk_rate;

	unsigned int		utmi_clk_rate;

	struct clk		*utmi_clk_src;

	struct regulator	*dwc3_gdsc;



	struct usb_phy		*hs_phy, *ss_phy;
@@ -988,7 +989,7 @@ static void dwc3_msm_update_ref_clk(struct dwc3_msm *mdwc) 
	}



	/* Refer to SNPS Databook Table 6-55 for calculations used */

	switch (mdwc->ref_clk_rate) {

	switch (mdwc->utmi_clk_rate) {

	case 19200000:

		guctl |= 52 << __ffs(DWC3_GUCTL_REFCLKPER);

		gfladj |= 12 << __ffs(DWC3_GFLADJ_REFCLK_240MHZ_DECR);
@@ -1003,8 +1004,8 @@ static void dwc3_msm_update_ref_clk(struct dwc3_msm *mdwc) 
		gfladj |= 2032 << __ffs(DWC3_GFLADJ_REFCLK_FLADJ);

		break;

	default:

		dev_warn(mdwc->dev, "Unsupported ref_clk_rate: %lu\n",

				mdwc->ref_clk_rate);

		dev_warn(mdwc->dev, "Unsupported utmi_clk_rate: %u\n",

				mdwc->utmi_clk_rate);

		break;

	}
@@ -2403,13 +2404,36 @@ static int dwc3_msm_probe(struct platform_device *pdev) 
	}

	clk_prepare_enable(mdwc->hsphy_sleep_clk);



	ret = of_property_read_u32(node, "qcom,utmi-clk-rate",

				   (u32 *)&mdwc->utmi_clk_rate);

	if (ret)

		mdwc->utmi_clk_rate = 19200000;



	mdwc->utmi_clk = devm_clk_get(&pdev->dev, "utmi_clk");

	if (IS_ERR(mdwc->utmi_clk)) {

		dev_err(&pdev->dev, "failed to get utmi_clk\n");

		ret = PTR_ERR(mdwc->utmi_clk);

		goto disable_hsphy_sleep_clk;

	}

	clk_set_rate(mdwc->utmi_clk, 19200000);



	if (mdwc->utmi_clk_rate == 24000000) {

		/*

		 * For setting utmi clock to 24MHz, first set 48MHz on parent

		 * clock "utmi_clk_src" and then set divider 2 on child branch

		 * "utmi_clk".

		 */

		mdwc->utmi_clk_src = devm_clk_get(&pdev->dev, "utmi_clk_src");

		if (IS_ERR(mdwc->utmi_clk_src)) {

			dev_err(&pdev->dev, "failed to get utmi_clk_src\n");

			ret = PTR_ERR(mdwc->utmi_clk_src);

			goto disable_hsphy_sleep_clk;

		}

		clk_set_rate(mdwc->utmi_clk_src, 48000000);

		/* 1 means divide utmi_clk_src by 2 */

		clk_set_rate(mdwc->utmi_clk, 1);

	} else {

		clk_set_rate(mdwc->utmi_clk, mdwc->utmi_clk_rate);

	}

	clk_prepare_enable(mdwc->utmi_clk);



	mdwc->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
@@ -2418,11 +2442,7 @@ static int dwc3_msm_probe(struct platform_device *pdev) 
		ret = PTR_ERR(mdwc->ref_clk);

		goto disable_utmi_clk;

	}

	ret = of_property_read_u32(node, "qcom,ref-clk-rate",

				   (u32 *)&mdwc->ref_clk_rate);

	if (ret)

		mdwc->ref_clk_rate = 19200000;

	clk_set_rate(mdwc->ref_clk, mdwc->ref_clk_rate);

	clk_set_rate(mdwc->ref_clk, 19200000);

	clk_prepare_enable(mdwc->ref_clk);



	mdwc->id_state = mdwc->ext_xceiv.id = DWC3_ID_FLOAT;