Loading drivers/gpu/msm/a4xx_reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -392,6 +392,8 @@ enum a4xx_sp_perfctr_sp_sel { /* UCHE register */ #define UCHE_TRAP_BASE_LO 0xe83 #define UCHE_TRAP_BASE_HI 0xe84 #define A4XX_UCHE_INVALIDATE0 0xe8a #define A4XX_UCHE_INVALIDATE1 0xe8b /* VSC registers */ #define A4XX_VSC_SIZE_ADDRESS 0xc01 Loading drivers/gpu/msm/adreno_a4xx.c +4 −0 Original line number Diff line number Diff line Loading @@ -237,6 +237,10 @@ const unsigned int a4xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = { A4XX_SP_VS_OBJ_START), ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_FS_OBJ_START_REG, A4XX_SP_FS_OBJ_START), ADRENO_REG_DEFINE(ADRENO_CP_UCHE_INVALIDATE0, A4XX_UCHE_INVALIDATE0), ADRENO_REG_DEFINE(ADRENO_CP_UCHE_INVALIDATE1, A4XX_UCHE_INVALIDATE1), }; static const struct adreno_vbif_data a420_vbif[] = { Loading drivers/gpu/msm/adreno_cp_parser.c +8 −0 Original line number Diff line number Diff line Loading @@ -618,6 +618,14 @@ static void ib_parse_type0(struct kgsl_device *device, unsigned int *ptr, ib_parse_vars->cp_addr_regs[ ADRENO_CP_ADDR_SP_FS_OBJ_START_REG] = ptr[i + 1]; else if ((offset == adreno_cp_parser_getreg(adreno_dev, ADRENO_CP_UCHE_INVALIDATE0)) || (offset == adreno_cp_parser_getreg(adreno_dev, ADRENO_CP_UCHE_INVALIDATE1))) adreno_ib_add_range(device, ptbase, ptr[i + 1] & 0xFFFFFFC0, 0, SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list); } } ib_add_type0_entries(device, ptbase, ib_obj_list, Loading drivers/gpu/msm/adreno_cp_parser.h +2 −0 Original line number Diff line number Diff line Loading @@ -101,6 +101,8 @@ enum adreno_cp_addr_regs { ADRENO_CP_ADDR_SP_FS_PVT_MEM_ADDR, ADRENO_CP_ADDR_SP_VS_OBJ_START_REG, ADRENO_CP_ADDR_SP_FS_OBJ_START_REG, ADRENO_CP_UCHE_INVALIDATE0, ADRENO_CP_UCHE_INVALIDATE1, ADRENO_CP_ADDR_MAX, }; Loading Loading
drivers/gpu/msm/a4xx_reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -392,6 +392,8 @@ enum a4xx_sp_perfctr_sp_sel { /* UCHE register */ #define UCHE_TRAP_BASE_LO 0xe83 #define UCHE_TRAP_BASE_HI 0xe84 #define A4XX_UCHE_INVALIDATE0 0xe8a #define A4XX_UCHE_INVALIDATE1 0xe8b /* VSC registers */ #define A4XX_VSC_SIZE_ADDRESS 0xc01 Loading
drivers/gpu/msm/adreno_a4xx.c +4 −0 Original line number Diff line number Diff line Loading @@ -237,6 +237,10 @@ const unsigned int a4xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = { A4XX_SP_VS_OBJ_START), ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_FS_OBJ_START_REG, A4XX_SP_FS_OBJ_START), ADRENO_REG_DEFINE(ADRENO_CP_UCHE_INVALIDATE0, A4XX_UCHE_INVALIDATE0), ADRENO_REG_DEFINE(ADRENO_CP_UCHE_INVALIDATE1, A4XX_UCHE_INVALIDATE1), }; static const struct adreno_vbif_data a420_vbif[] = { Loading
drivers/gpu/msm/adreno_cp_parser.c +8 −0 Original line number Diff line number Diff line Loading @@ -618,6 +618,14 @@ static void ib_parse_type0(struct kgsl_device *device, unsigned int *ptr, ib_parse_vars->cp_addr_regs[ ADRENO_CP_ADDR_SP_FS_OBJ_START_REG] = ptr[i + 1]; else if ((offset == adreno_cp_parser_getreg(adreno_dev, ADRENO_CP_UCHE_INVALIDATE0)) || (offset == adreno_cp_parser_getreg(adreno_dev, ADRENO_CP_UCHE_INVALIDATE1))) adreno_ib_add_range(device, ptbase, ptr[i + 1] & 0xFFFFFFC0, 0, SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list); } } ib_add_type0_entries(device, ptbase, ib_obj_list, Loading
drivers/gpu/msm/adreno_cp_parser.h +2 −0 Original line number Diff line number Diff line Loading @@ -101,6 +101,8 @@ enum adreno_cp_addr_regs { ADRENO_CP_ADDR_SP_FS_PVT_MEM_ADDR, ADRENO_CP_ADDR_SP_VS_OBJ_START_REG, ADRENO_CP_ADDR_SP_FS_OBJ_START_REG, ADRENO_CP_UCHE_INVALIDATE0, ADRENO_CP_UCHE_INVALIDATE1, ADRENO_CP_ADDR_MAX, }; Loading