Loading arch/arm/boot/dts/qcom/msm8994.dtsi +7 −2 Original line number Diff line number Diff line Loading @@ -1441,11 +1441,16 @@ mmpll4_dig-supply = <&pm8994_s1_corner>; mmpll4_analog-supply = <&pm8994_l12>; clock-names = "xo", "gpll0", "mmssnoc_ahb", "oxili_gfx3d_clk"; "oxili_gfx3d_clk", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src"; clocks = <&clock_rpm clk_cxo_clk_src>, <&clock_gcc clk_gpll0_out_mmsscc>, <&clock_rpm clk_mmssnoc_ahb_clk>, <&clock_rpm clk_oxili_gfx3d_clk_src>; <&clock_rpm clk_oxili_gfx3d_clk_src>, <&mdss_dsi0_pll clk_pixel_clk_src>, <&mdss_dsi0_pll clk_pixel_clk_src>, <&mdss_dsi0_pll clk_byte_clk_src>, <&mdss_dsi0_pll clk_byte_clk_src>; #clock-cells = <1>; }; Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +7 −2 Original line number Diff line number Diff line Loading @@ -1441,11 +1441,16 @@ mmpll4_dig-supply = <&pm8994_s1_corner>; mmpll4_analog-supply = <&pm8994_l12>; clock-names = "xo", "gpll0", "mmssnoc_ahb", "oxili_gfx3d_clk"; "oxili_gfx3d_clk", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src"; clocks = <&clock_rpm clk_cxo_clk_src>, <&clock_gcc clk_gpll0_out_mmsscc>, <&clock_rpm clk_mmssnoc_ahb_clk>, <&clock_rpm clk_oxili_gfx3d_clk_src>; <&clock_rpm clk_oxili_gfx3d_clk_src>, <&mdss_dsi0_pll clk_pixel_clk_src>, <&mdss_dsi0_pll clk_pixel_clk_src>, <&mdss_dsi0_pll clk_byte_clk_src>, <&mdss_dsi0_pll clk_byte_clk_src>; #clock-cells = <1>; }; Loading