ARM: S3C24XX: Add clkdev support (e83626f2) · Commits · e / devices / android_kernel_sony_msm8994

arch/arm/Kconfig

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -682,6 +682,7 @@ config ARCH_S3C2410
	select GENERIC_GPIO		select GENERIC_GPIO
	select ARCH_HAS_CPUFREQ		select ARCH_HAS_CPUFREQ
	select HAVE_CLK		select HAVE_CLK
			select CLKDEV_LOOKUP
	select ARCH_USES_GETTIMEOFFSET		select ARCH_USES_GETTIMEOFFSET
	select HAVE_S3C2410_I2C if I2C		select HAVE_S3C2410_I2C if I2C
	help		help

arch/arm/mach-s3c2412/clock.c

+3 −33

Original line number	Original line	Diff line number	Diff line
	@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)

	static struct clk clk_erefclk = {		static struct clk clk_erefclk = {
	.name = "erefclk",		.name = "erefclk",
	.id = -1,
	};		};

	static struct clk clk_urefclk = {		static struct clk clk_urefclk = {
	.name = "urefclk",		.name = "urefclk",
	.id = -1,
	};		};

	static int s3c2412_setparent_usysclk(struct clk clk, struct clk parent)		static int s3c2412_setparent_usysclk(struct clk clk, struct clk parent)
	@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk clk, struct clk parent)

	static struct clk clk_usysclk = {		static struct clk clk_usysclk = {
	.name = "usysclk",		.name = "usysclk",
	.id = -1,
	.parent = &clk_xtal,		.parent = &clk_xtal,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.set_parent = s3c2412_setparent_usysclk,		.set_parent = s3c2412_setparent_usysclk,
	@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
	static struct clk clk_mrefclk = {		static struct clk clk_mrefclk = {
	.name = "mrefclk",		.name = "mrefclk",
	.parent = &clk_xtal,		.parent = &clk_xtal,
	.id = -1,
	};		};

	static struct clk clk_mdivclk = {		static struct clk clk_mdivclk = {
	.name = "mdivclk",		.name = "mdivclk",
	.parent = &clk_xtal,		.parent = &clk_xtal,
	.id = -1,
	};		};

	static int s3c2412_setparent_usbsrc(struct clk clk, struct clk parent)		static int s3c2412_setparent_usbsrc(struct clk clk, struct clk parent)
	@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)

	static struct clk clk_usbsrc = {		static struct clk clk_usbsrc = {
	.name = "usbsrc",		.name = "usbsrc",
	.id = -1,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.get_rate = s3c2412_getrate_usbsrc,		.get_rate = s3c2412_getrate_usbsrc,
	.set_rate = s3c2412_setrate_usbsrc,		.set_rate = s3c2412_setrate_usbsrc,
	@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk clk, struct clk parent)

	static struct clk clk_msysclk = {		static struct clk clk_msysclk = {
	.name = "msysclk",		.name = "msysclk",
	.id = -1,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.set_parent = s3c2412_setparent_msysclk,		.set_parent = s3c2412_setparent_msysclk,
	},		},
	@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk clk, struct clk parent)

	static struct clk clk_armclk = {		static struct clk clk_armclk = {
	.name = "armclk",		.name = "armclk",
	.id = -1,
	.parent = &clk_msysclk,		.parent = &clk_msysclk,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.set_parent = s3c2412_setparent_armclk,		.set_parent = s3c2412_setparent_armclk,
	@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)

	static struct clk clk_uart = {		static struct clk clk_uart = {
	.name = "uartclk",		.name = "uartclk",
	.id = -1,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.get_rate = s3c2412_getrate_uart,		.get_rate = s3c2412_getrate_uart,
	.set_rate = s3c2412_setrate_uart,		.set_rate = s3c2412_setrate_uart,
	@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)

	static struct clk clk_i2s = {		static struct clk clk_i2s = {
	.name = "i2sclk",		.name = "i2sclk",
	.id = -1,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.get_rate = s3c2412_getrate_i2s,		.get_rate = s3c2412_getrate_i2s,
	.set_rate = s3c2412_setrate_i2s,		.set_rate = s3c2412_setrate_i2s,
	@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)

	static struct clk clk_cam = {		static struct clk clk_cam = {
	.name = "camif-upll", /* same as 2440 name */		.name = "camif-upll", /* same as 2440 name */
	.id = -1,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.get_rate = s3c2412_getrate_cam,		.get_rate = s3c2412_getrate_cam,
	.set_rate = s3c2412_setrate_cam,		.set_rate = s3c2412_setrate_cam,
	@@ -463,37 +452,31 @@ static struct clk clk_cam = {
	static struct clk init_clocks_disable[] = {		static struct clk init_clocks_disable[] = {
	{		{
	.name = "nand",		.name = "nand",
	.id = -1,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_NAND,		.ctrlbit = S3C2412_CLKCON_NAND,
	}, {		}, {
	.name = "sdi",		.name = "sdi",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_SDI,		.ctrlbit = S3C2412_CLKCON_SDI,
	}, {		}, {
	.name = "adc",		.name = "adc",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_ADC,		.ctrlbit = S3C2412_CLKCON_ADC,
	}, {		}, {
	.name = "i2c",		.name = "i2c",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_IIC,		.ctrlbit = S3C2412_CLKCON_IIC,
	}, {		}, {
	.name = "iis",		.name = "iis",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_IIS,		.ctrlbit = S3C2412_CLKCON_IIS,
	}, {		}, {
	.name = "spi",		.name = "spi",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_SPI,		.ctrlbit = S3C2412_CLKCON_SPI,
	@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
	static struct clk init_clocks[] = {		static struct clk init_clocks[] = {
	{		{
	.name = "dma",		.name = "dma",
	.id = 0,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_DMA0,		.ctrlbit = S3C2412_CLKCON_DMA0,
	}, {		}, {
	.name = "dma",		.name = "dma",
	.id = 1,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_DMA1,		.ctrlbit = S3C2412_CLKCON_DMA1,
	}, {		}, {
	.name = "dma",		.name = "dma",
	.id = 2,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_DMA2,		.ctrlbit = S3C2412_CLKCON_DMA2,
	}, {		}, {
	.name = "dma",		.name = "dma",
	.id = 3,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_DMA3,		.ctrlbit = S3C2412_CLKCON_DMA3,
	}, {		}, {
	.name = "lcd",		.name = "lcd",
	.id = -1,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_LCDC,		.ctrlbit = S3C2412_CLKCON_LCDC,
	}, {		}, {
	.name = "gpio",		.name = "gpio",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_GPIO,		.ctrlbit = S3C2412_CLKCON_GPIO,
	}, {		}, {
	.name = "usb-host",		.name = "usb-host",
	.id = -1,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_USBH,		.ctrlbit = S3C2412_CLKCON_USBH,
	}, {		}, {
	.name = "usb-device",		.name = "usb-device",
	.id = -1,
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_USBD,		.ctrlbit = S3C2412_CLKCON_USBD,
	}, {		}, {
	.name = "timers",		.name = "timers",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_PWMT,		.ctrlbit = S3C2412_CLKCON_PWMT,
	}, {		}, {
	.name = "uart",		.name = "uart",
	.id = 0,		.devname = "s3c2412-uart.0",
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_UART0,		.ctrlbit = S3C2412_CLKCON_UART0,
	}, {		}, {
	.name = "uart",		.name = "uart",
	.id = 1,		.devname = "s3c2412-uart.1",
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_UART1,		.ctrlbit = S3C2412_CLKCON_UART1,
	}, {		}, {
	.name = "uart",		.name = "uart",
	.id = 2,		.devname = "s3c2412-uart.2",
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_UART2,		.ctrlbit = S3C2412_CLKCON_UART2,
	}, {		}, {
	.name = "rtc",		.name = "rtc",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_RTC,		.ctrlbit = S3C2412_CLKCON_RTC,
	}, {		}, {
	.name = "watchdog",		.name = "watchdog",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.ctrlbit = 0,		.ctrlbit = 0,
	}, {		}, {
	.name = "usb-bus-gadget",		.name = "usb-bus-gadget",
	.id = -1,
	.parent = &clk_usb_bus,		.parent = &clk_usb_bus,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_USB_DEV48,		.ctrlbit = S3C2412_CLKCON_USB_DEV48,
	}, {		}, {
	.name = "usb-bus-host",		.name = "usb-bus-host",
	.id = -1,
	.parent = &clk_usb_bus,		.parent = &clk_usb_bus,
	.enable = s3c2412_clkcon_enable,		.enable = s3c2412_clkcon_enable,
	.ctrlbit = S3C2412_CLKCON_USB_HOST48,		.ctrlbit = S3C2412_CLKCON_USB_HOST48,

arch/arm/mach-s3c2416/clock.c

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
	[0] = {		[0] = {
	.clk = {		.clk = {
	.name = "hsmmc-div",		.name = "hsmmc-div",
	.id = 0,		.devname = "s3c-sdhci.0",
	.parent = &clk_esysclk.clk,		.parent = &clk_esysclk.clk,
	},		},
	.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },		.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
	@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
	[1] = {		[1] = {
	.clk = {		.clk = {
	.name = "hsmmc-div",		.name = "hsmmc-div",
	.id = 1,		.devname = "s3c-sdhci.1",
	.parent = &clk_esysclk.clk,		.parent = &clk_esysclk.clk,
	},		},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
	@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
	static struct clksrc_clk hsmmc_mux[] = {		static struct clksrc_clk hsmmc_mux[] = {
	[0] = {		[0] = {
	.clk = {		.clk = {
	.id = 0,
	.name = "hsmmc-if",		.name = "hsmmc-if",
			.devname = "s3c-sdhci.0",
	.ctrlbit = (1 << 6),		.ctrlbit = (1 << 6),
	.enable = s3c2443_clkcon_enable_s,		.enable = s3c2443_clkcon_enable_s,
	},		},
	@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
	},		},
	[1] = {		[1] = {
	.clk = {		.clk = {
	.id = 1,
	.name = "hsmmc-if",		.name = "hsmmc-if",
			.devname = "s3c-sdhci.1",
	.ctrlbit = (1 << 12),		.ctrlbit = (1 << 12),
	.enable = s3c2443_clkcon_enable_s,		.enable = s3c2443_clkcon_enable_s,
	},		},
	@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {

	static struct clk hsmmc0_clk = {		static struct clk hsmmc0_clk = {
	.name = "hsmmc",		.name = "hsmmc",
	.id = 0,		.devname = "s3c-sdhci.0",
	.parent = &clk_h,		.parent = &clk_h,
	.enable = s3c2443_clkcon_enable_h,		.enable = s3c2443_clkcon_enable_h,
	.ctrlbit = S3C2416_HCLKCON_HSMMC0,		.ctrlbit = S3C2416_HCLKCON_HSMMC0,

arch/arm/mach-s3c2440/clock.c

+0 −3

Original line number	Original line	Diff line number	Diff line
	@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)

	static struct clk s3c2440_clk_cam = {		static struct clk s3c2440_clk_cam = {
	.name = "camif",		.name = "camif",
	.id = -1,
	.enable = s3c2410_clkcon_enable,		.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2440_CLKCON_CAMERA,		.ctrlbit = S3C2440_CLKCON_CAMERA,
	};		};

	static struct clk s3c2440_clk_cam_upll = {		static struct clk s3c2440_clk_cam_upll = {
	.name = "camif-upll",		.name = "camif-upll",
	.id = -1,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.set_rate = s3c2440_camif_upll_setrate,		.set_rate = s3c2440_camif_upll_setrate,
	.round_rate = s3c2440_camif_upll_round,		.round_rate = s3c2440_camif_upll_round,
	@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {

	static struct clk s3c2440_clk_ac97 = {		static struct clk s3c2440_clk_ac97 = {
	.name = "ac97",		.name = "ac97",
	.id = -1,
	.enable = s3c2410_clkcon_enable,		.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2440_CLKCON_CAMERA,		.ctrlbit = S3C2440_CLKCON_CAMERA,
	};		};

arch/arm/mach-s3c2443/clock.c

+4 −12

Original line number	Original line	Diff line number	Diff line
	@@ -59,7 +59,6 @@

	static struct clk clk_i2s_ext = {		static struct clk clk_i2s_ext = {
	.name = "i2s-ext",		.name = "i2s-ext",
	.id = -1,
	};		};

	/* armdiv		/* armdiv
	@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)

	static struct clk clk_armdiv = {		static struct clk clk_armdiv = {
	.name = "armdiv",		.name = "armdiv",
	.id = -1,
	.parent = &clk_msysclk.clk,		.parent = &clk_msysclk.clk,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	.round_rate = s3c2443_armclk_roundrate,		.round_rate = s3c2443_armclk_roundrate,
	@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
	static struct clksrc_clk clk_arm = {		static struct clksrc_clk clk_arm = {
	.clk = {		.clk = {
	.name = "armclk",		.name = "armclk",
	.id = -1,
	},		},
	.sources = &(struct clksrc_sources) {		.sources = &(struct clksrc_sources) {
	.sources = clk_arm_sources,		.sources = clk_arm_sources,
	@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
	static struct clksrc_clk clk_hsspi = {		static struct clksrc_clk clk_hsspi = {
	.clk = {		.clk = {
	.name = "hsspi",		.name = "hsspi",
	.id = -1,
	.parent = &clk_esysclk.clk,		.parent = &clk_esysclk.clk,
	.ctrlbit = S3C2443_SCLKCON_HSSPICLK,		.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
	.enable = s3c2443_clkcon_enable_s,		.enable = s3c2443_clkcon_enable_s,
	@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
	static struct clksrc_clk clk_hsmmc_div = {		static struct clksrc_clk clk_hsmmc_div = {
	.clk = {		.clk = {
	.name = "hsmmc-div",		.name = "hsmmc-div",
	.id = 1,		.devname = "s3c-sdhci.1",
	.parent = &clk_esysclk.clk,		.parent = &clk_esysclk.clk,
	},		},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
	@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)

	static struct clk clk_hsmmc = {		static struct clk clk_hsmmc = {
	.name = "hsmmc-if",		.name = "hsmmc-if",
	.id = 1,		.devname = "s3c-sdhci.1",
	.parent = &clk_hsmmc_div.clk,		.parent = &clk_hsmmc_div.clk,
	.enable = s3c2443_enable_hsmmc,		.enable = s3c2443_enable_hsmmc,
	.ops = &(struct clk_ops) {		.ops = &(struct clk_ops) {
	@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
	static struct clksrc_clk clk_i2s_eplldiv = {		static struct clksrc_clk clk_i2s_eplldiv = {
	.clk = {		.clk = {
	.name = "i2s-eplldiv",		.name = "i2s-eplldiv",
	.id = -1,
	.parent = &clk_esysclk.clk,		.parent = &clk_esysclk.clk,
	},		},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
	@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
	static struct clksrc_clk clk_i2s = {		static struct clksrc_clk clk_i2s = {
	.clk = {		.clk = {
	.name = "i2s-if",		.name = "i2s-if",
	.id = -1,
	.ctrlbit = S3C2443_SCLKCON_I2SCLK,		.ctrlbit = S3C2443_SCLKCON_I2SCLK,
	.enable = s3c2443_clkcon_enable_s,		.enable = s3c2443_clkcon_enable_s,

	@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
	static struct clk init_clocks_off[] = {		static struct clk init_clocks_off[] = {
	{		{
	.name = "sdi",		.name = "sdi",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2443_clkcon_enable_p,		.enable = s3c2443_clkcon_enable_p,
	.ctrlbit = S3C2443_PCLKCON_SDI,		.ctrlbit = S3C2443_PCLKCON_SDI,
	}, {		}, {
	.name = "iis",		.name = "iis",
	.id = -1,
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2443_clkcon_enable_p,		.enable = s3c2443_clkcon_enable_p,
	.ctrlbit = S3C2443_PCLKCON_IIS,		.ctrlbit = S3C2443_PCLKCON_IIS,
	}, {		}, {
	.name = "spi",		.name = "spi",
	.id = 0,		.devname = "s3c2410-spi.0",
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2443_clkcon_enable_p,		.enable = s3c2443_clkcon_enable_p,
	.ctrlbit = S3C2443_PCLKCON_SPI0,		.ctrlbit = S3C2443_PCLKCON_SPI0,
	}, {		}, {
	.name = "spi",		.name = "spi",
	.id = 1,		.devname = "s3c2410-spi.1",
	.parent = &clk_p,		.parent = &clk_p,
	.enable = s3c2443_clkcon_enable_p,		.enable = s3c2443_clkcon_enable_p,
	.ctrlbit = S3C2443_PCLKCON_SPI1,		.ctrlbit = S3C2443_PCLKCON_SPI1,