Loading arch/arm/boot/dts/apq8084.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -1804,7 +1804,7 @@ qcom,prim-auxpcm-gpio-sync = <&msmgpio 88 0>; qcom,prim-auxpcm-gpio-din = <&msmgpio 89 0>; qcom,prim-auxpcm-gpio-dout = <&msmgpio 90 0>; qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; qcom,prim-auxpcm-gpio-set = "prim-gpio-tert"; qcom,sec-auxpcm-gpio-clk = <&msmgpio 82 0>; qcom,sec-auxpcm-gpio-sync = <&msmgpio 83 0>; qcom,sec-auxpcm-gpio-din = <&msmgpio 84 0>; Loading sound/soc/msm/apq8084.c +4 −4 Original line number Diff line number Diff line Loading @@ -54,10 +54,10 @@ static int apq8084_auxpcm_rate = 8000; #define LO_4_SPK_AMP 0x8 #define LPAIF_OFFSET 0xFE000000 #define LPAIF_PRI_MODE_MUXSEL (LPAIF_OFFSET + 0x2B000) #define LPAIF_SEC_MODE_MUXSEL (LPAIF_OFFSET + 0x2C000) #define LPAIF_TER_MODE_MUXSEL (LPAIF_OFFSET + 0x2D000) #define LPAIF_QUAD_MODE_MUXSEL (LPAIF_OFFSET + 0x2E000) #define LPAIF_PRI_MODE_MUXSEL (LPAIF_OFFSET + 0x34000) #define LPAIF_SEC_MODE_MUXSEL (LPAIF_OFFSET + 0x35000) #define LPAIF_TER_MODE_MUXSEL (LPAIF_OFFSET + 0x36000) #define LPAIF_QUAD_MODE_MUXSEL (LPAIF_OFFSET + 0x37000) #define I2S_PCM_SEL 1 #define I2S_PCM_SEL_OFFSET 1 Loading Loading
arch/arm/boot/dts/apq8084.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -1804,7 +1804,7 @@ qcom,prim-auxpcm-gpio-sync = <&msmgpio 88 0>; qcom,prim-auxpcm-gpio-din = <&msmgpio 89 0>; qcom,prim-auxpcm-gpio-dout = <&msmgpio 90 0>; qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; qcom,prim-auxpcm-gpio-set = "prim-gpio-tert"; qcom,sec-auxpcm-gpio-clk = <&msmgpio 82 0>; qcom,sec-auxpcm-gpio-sync = <&msmgpio 83 0>; qcom,sec-auxpcm-gpio-din = <&msmgpio 84 0>; Loading
sound/soc/msm/apq8084.c +4 −4 Original line number Diff line number Diff line Loading @@ -54,10 +54,10 @@ static int apq8084_auxpcm_rate = 8000; #define LO_4_SPK_AMP 0x8 #define LPAIF_OFFSET 0xFE000000 #define LPAIF_PRI_MODE_MUXSEL (LPAIF_OFFSET + 0x2B000) #define LPAIF_SEC_MODE_MUXSEL (LPAIF_OFFSET + 0x2C000) #define LPAIF_TER_MODE_MUXSEL (LPAIF_OFFSET + 0x2D000) #define LPAIF_QUAD_MODE_MUXSEL (LPAIF_OFFSET + 0x2E000) #define LPAIF_PRI_MODE_MUXSEL (LPAIF_OFFSET + 0x34000) #define LPAIF_SEC_MODE_MUXSEL (LPAIF_OFFSET + 0x35000) #define LPAIF_TER_MODE_MUXSEL (LPAIF_OFFSET + 0x36000) #define LPAIF_QUAD_MODE_MUXSEL (LPAIF_OFFSET + 0x37000) #define I2S_PCM_SEL 1 #define I2S_PCM_SEL_OFFSET 1 Loading