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Commit e5a87e75 authored by Aparna Das's avatar Aparna Das
Browse files

jtagv8: fix debug and etm registers save and restore path 



Locking OS Double Lock during Debug register save sequence can make
the trace unit behave as if it is in no power state. To avoid this
save ETM registers before the trace unit enters this state during
Debug register save sequence and also restore ETM registers only
after OS Double Lock is	unlocked in Debug register restore sequence.

Change-Id: Ic121acef01908406f0ab33b623bac8acd9d2e586
Signed-off-by: default avatarAparna Das <adas@codeaurora.org>
parent d81481d4

drivers/soc/qcom/jtagv8.c

+14 −2
Original line number Diff line number Diff line
@@ -396,6 +396,9 @@ static inline void dbg_save_state(int cpu) 
		dbg.state[i++] =  (uint32_t)dbg_readl(OSDTRRX_EL1);

		dbg.state[i++] =  (uint32_t)dbg_readl(OSDTRTX_EL1);



		/* Set the OS double lock */

		isb();

		dbg_write(0x1, OSDLR_EL1);

		isb();

		break;

	default:
@@ -412,10 +415,14 @@ static inline void dbg_restore_state(int cpu) 


	switch (dbg.arch) {

	case ARM_DEBUG_ARCH_V8:

		/* Clear the OS double lock */

		isb();

		dbg_write(0x0, OSDLR_EL1);

		isb();



		/* Set OS lock. Lock will already be set after power collapse

		 * but this write is included to ensure it is set.

		 */

		isb();

		dbg_write(0x1, OSLAR_EL1);

		isb();
@@ -791,6 +798,11 @@ static inline void dbg_restore_state(int cpu) 


	switch (dbg.arch) {

	case ARM_DEBUG_ARCH_V8:

		/* Clear the OS double lock */

		isb();

		dbg_write(0x0, DBGOSDLR);

		isb();



		/* Set OS lock. Lock will already be set after power collapse

		 * but this write is included to ensure it is set.

		 */
@@ -859,9 +871,9 @@ void msm_jtag_save_state(void) 
	/* ensure counter is updated before moving forward */

	mb();



	msm_jtag_mm_save_state();

	if (dbg.save_restore_enabled)

		dbg_save_state(cpu);

	msm_jtag_mm_save_state();

}

EXPORT_SYMBOL(msm_jtag_save_state);