Merge "power: bcl_peripheral: Fix Ibat MAX and Vbat MIN read sequence" (e4cd7661) · Commits · e / devices / android_kernel_sony_msm8994

drivers/power/bcl_peripheral.c

+68 −46

Original line number	Diff line number	Diff line
		@@ -38,6 +38,8 @@
		#define BCL_IBAT_CP_VALUE 0x57
		#define BCL_VBAT_MIN 0x58
		#define BCL_IBAT_MAX 0x59
		#define BCL_VBAT_MIN_CP 0x5A
		#define BCL_IBAT_MAX_CP 0x5B
		#define BCL_V_GAIN_BAT 0x60
		#define BCL_I_GAIN_RSENSE 0x61
		#define BCL_I_OFFSET_RSENSE 0x62
		@@ -54,6 +56,9 @@


		#define BCL_READ_RETRY_LIMIT 3
		#define VAL_CP_REG_BUF_LEN 3
		#define VAL_REG_BUF_OFFSET 0
		#define VAL_CP_REG_BUF_OFFSET 2

		#define READ_CONV_FACTOR(_node, _key, _val, _ret, _dest) do { \
		_ret = of_property_read_u32(_node, _key, &_val); \
		@@ -104,7 +109,7 @@ static struct bcl_device *bcl_perph;
		static DEFINE_MUTEX(bcl_access_mutex);
		static DEFINE_MUTEX(bcl_enable_mutex);

		static int bcl_read_register(int16_t reg_offset, uint8_t *data)
		static int bcl_read_multi_register(int16_t reg_offset, uint8_t *data, int len)
		{
		int ret = 0;

		@@ -114,7 +119,7 @@ static int bcl_read_register(int16_t reg_offset, uint8_t *data)
		}
		ret = spmi_ext_register_readl(bcl_perph->spmi->ctrl,
		bcl_perph->slave_id, (bcl_perph->base_addr + reg_offset),
		data, 1);
		data, len);
		if (ret < 0) {
		pr_err("Error reading register %d. err:%d", reg_offset, ret);
		return ret;
		@@ -123,6 +128,11 @@ static int bcl_read_register(int16_t reg_offset, uint8_t *data)
		return ret;
		}

		static int bcl_read_register(int16_t reg_offset, uint8_t *data)
		{
		return bcl_read_multi_register(reg_offset, data, 1);
		}

		static int bcl_write_register(int16_t reg_offset, uint8_t data)
		{
		int ret = 0;
		@@ -370,18 +380,27 @@ static int bcl_clear_ibat_max(void)

		static int bcl_read_ibat_max(int *adc_value)
		{
		int ret = 0;
		int8_t val = 0;
		int ret = 0, timeout = 0;
		int8_t val[VAL_CP_REG_BUF_LEN] = {0};

		*adc_value = (int)val;
		ret = bcl_read_register(BCL_IBAT_MAX, &val);
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		do {
		ret = bcl_read_multi_register(BCL_IBAT_MAX, val,
		VAL_CP_REG_BUF_LEN);
		if (ret) {
		pr_err("BCL register read error. err:%d\n", ret);
		goto bcl_read_exit;
		}
		*adc_value = (int)val;
		} while (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]
		&& timeout++ < BCL_READ_RETRY_LIMIT);
		if (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]) {
		ret = -ENODEV;
		goto bcl_read_exit;
		}
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		convert_adc_to_ibat_val(adc_value);
		pr_debug("Ibat Max:%d. ADC_val:%d\n", *adc_value, val);
		pr_debug("Ibat Max:%d. ADC_val:%d\n", *adc_value,
		val[VAL_REG_BUF_OFFSET]);

		bcl_read_exit:
		return ret;
		@@ -389,18 +408,27 @@ bcl_read_exit:

		static int bcl_read_vbat_min(int *adc_value)
		{
		int ret = 0;
		int8_t val = 0;
		int ret = 0, timeout = 0;
		int8_t val[VAL_CP_REG_BUF_LEN] = {0};

		*adc_value = (int)val;
		ret = bcl_read_register(BCL_VBAT_MIN, &val);
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		do {
		ret = bcl_read_multi_register(BCL_VBAT_MIN, val,
		VAL_CP_REG_BUF_LEN);
		if (ret) {
		pr_err("BCL register read error. err:%d\n", ret);
		goto bcl_read_exit;
		}
		*adc_value = (int)val;
		} while (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]
		&& timeout++ < BCL_READ_RETRY_LIMIT);
		if (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]) {
		ret = -ENODEV;
		goto bcl_read_exit;
		}
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		convert_adc_to_vbat_val(adc_value);
		pr_debug("Vbat Min:%d. ADC_val:%d\n", *adc_value, val);
		pr_debug("Vbat Min:%d. ADC_val:%d\n", *adc_value,
		val[VAL_REG_BUF_OFFSET]);

		bcl_read_exit:
		return ret;
		@@ -409,29 +437,26 @@ bcl_read_exit:
		static int bcl_read_ibat(int *adc_value)
		{
		int ret = 0, timeout = 0;
		int8_t val = 0, val_cp = 0;
		int8_t val[VAL_CP_REG_BUF_LEN] = {0};

		*adc_value = (int)val;
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		do {
		ret = bcl_read_register(BCL_IBAT_VALUE, &val);
		ret = bcl_read_multi_register(BCL_IBAT_VALUE, val,
		VAL_CP_REG_BUF_LEN);
		if (ret) {
		pr_err("BCL register read error. err:%d\n", ret);
		goto bcl_read_exit;
		}
		ret = bcl_read_register(BCL_IBAT_CP_VALUE, &val_cp);
		if (ret) {
		pr_err("BCL compare register read error. err:%d\n",
		ret);
		goto bcl_read_exit;
		}
		} while (val != val_cp && timeout++ < BCL_READ_RETRY_LIMIT);
		if (val != val_cp) {
		ret = -1;
		} while (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]
		&& timeout++ < BCL_READ_RETRY_LIMIT);
		if (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]) {
		ret = -ENODEV;
		goto bcl_read_exit;
		}
		*adc_value = (int)val;
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		convert_adc_to_ibat_val(adc_value);
		pr_debug("Read Ibat:%d. ADC_val:%d\n", *adc_value, val);
		pr_debug("Read Ibat:%d. ADC_val:%d\n", *adc_value,
		val[VAL_REG_BUF_OFFSET]);

		bcl_read_exit:
		return ret;
		@@ -440,29 +465,26 @@ bcl_read_exit:
		static int bcl_read_vbat(int *adc_value)
		{
		int ret = 0, timeout = 0;
		int8_t val = 0, val_cp = 0;
		int8_t val[VAL_CP_REG_BUF_LEN] = {0};

		*adc_value = (int)val;
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		do {
		ret = bcl_read_register(BCL_VBAT_VALUE, &val);
		ret = bcl_read_multi_register(BCL_VBAT_VALUE, val,
		VAL_CP_REG_BUF_LEN);
		if (ret) {
		pr_err("BCL register read error. err:%d\n", ret);
		goto bcl_read_exit;
		}
		ret = bcl_read_register(BCL_VBAT_CP_VALUE, &val_cp);
		if (ret) {
		pr_err("BCL compare register read error. err:%d\n",
		ret);
		goto bcl_read_exit;
		}
		} while (val != val_cp && timeout++ < BCL_READ_RETRY_LIMIT);
		if (val != val_cp) {
		ret = -1;
		} while (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]
		&& timeout++ < BCL_READ_RETRY_LIMIT);
		if (val[VAL_REG_BUF_OFFSET] != val[VAL_CP_REG_BUF_OFFSET]) {
		ret = -ENODEV;
		goto bcl_read_exit;
		}
		*adc_value = (int)val;
		*adc_value = (int)val[VAL_REG_BUF_OFFSET];
		convert_adc_to_vbat_val(adc_value);
		pr_debug("Read Vbat:%d. ADC_val:%d\n", *adc_value, val);
		pr_debug("Read Vbat:%d. ADC_val:%d\n", *adc_value,
		val[VAL_REG_BUF_OFFSET]);

		bcl_read_exit:
		return ret;