Loading arch/arm/boot/dts/qcom/msm8909.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -244,8 +244,9 @@ qcom,clock-a7@0b011050 { compatible = "qcom,clock-a53-8916"; reg = <0x0b011050 0x8>; reg-names = "rcg-base"; reg = <0x0b011050 0x8>, <0x0005c004 0x8>; reg-names = "rcg-base", "efuse"; qcom,safe-freq = < 400000000 >; cpu-vdd-supply = <&pm8909_s1_corner_ao>; clocks = <&clock_gcc clk_gpll0_ao_clk_src>, Loading @@ -255,7 +256,7 @@ < 0 0>, < 400000000 4>, < 800000000 5>, < 1248000000 7>; < 1305600000 7>; }; Loading Loading @@ -295,7 +296,8 @@ < 998400 >, < 1094400 >, < 1190400 >, < 1248000 >; < 1248000 >, < 1305600 >; }; Loading Loading
arch/arm/boot/dts/qcom/msm8909.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -244,8 +244,9 @@ qcom,clock-a7@0b011050 { compatible = "qcom,clock-a53-8916"; reg = <0x0b011050 0x8>; reg-names = "rcg-base"; reg = <0x0b011050 0x8>, <0x0005c004 0x8>; reg-names = "rcg-base", "efuse"; qcom,safe-freq = < 400000000 >; cpu-vdd-supply = <&pm8909_s1_corner_ao>; clocks = <&clock_gcc clk_gpll0_ao_clk_src>, Loading @@ -255,7 +256,7 @@ < 0 0>, < 400000000 4>, < 800000000 5>, < 1248000000 7>; < 1305600000 7>; }; Loading Loading @@ -295,7 +296,8 @@ < 998400 >, < 1094400 >, < 1190400 >, < 1248000 >; < 1248000 >, < 1305600 >; }; Loading