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Commit e337b6ee authored by Xiaozhe Shi's avatar Xiaozhe Shi
Browse files

power: qpnp-charger: only apply ibat-loop fix when battery is present 



An issue was observed where the device could continuously reset when
the battery pins are left floating and the ibat-loop was disabled.

Fix this by only applying the ibat-loop workaround when the device has
a battery present.

Change-Id: I273b8fe3dc3c99e9bbb619e8e15abfd4c298366e
Signed-off-by: default avatarXiaozhe Shi <xiaozhes@codeaurora.org>
parent 5f4d31f2

drivers/power/qpnp-charger.c

+56 −17
Original line number Diff line number Diff line
@@ -1529,11 +1529,13 @@ static irqreturn_t 
qpnp_chg_bat_if_batt_temp_irq_handler(int irq, void *_chip)

{

	struct qpnp_chg_chip *chip = _chip;

	int batt_temp_good, rc;

	int batt_temp_good, batt_present, rc;



	batt_temp_good = qpnp_chg_is_batt_temp_ok(chip);

	pr_debug("batt-temp triggered: %d\n", batt_temp_good);



	batt_present = qpnp_chg_is_batt_present(chip);

	if (batt_present) {

		rc = qpnp_chg_masked_write(chip,

			chip->buck_base + SEC_ACCESS,

			0xFF,
@@ -1551,6 +1553,7 @@ qpnp_chg_bat_if_batt_temp_irq_handler(int irq, void *_chip) 
			pr_err("failed to write COMP_OVR1 rc=%d\n", rc);

			return rc;

		}

	}



	pr_debug("psy changed batt_psy\n");

	power_supply_changed(&chip->batt_psy);
@@ -1561,15 +1564,51 @@ static irqreturn_t 
qpnp_chg_bat_if_batt_pres_irq_handler(int irq, void *_chip)

{

	struct qpnp_chg_chip *chip = _chip;

	int batt_present;

	int batt_present, batt_temp_good, rc;



	batt_present = qpnp_chg_is_batt_present(chip);

	pr_debug("batt-pres triggered: %d\n", batt_present);



	if (chip->batt_present ^ batt_present) {

		if (batt_present) {

			batt_temp_good = qpnp_chg_is_batt_temp_ok(chip);

			rc = qpnp_chg_masked_write(chip,

				chip->buck_base + SEC_ACCESS,

				0xFF,

				0xA5, 1);

			if (rc) {

				pr_err("failed to write SEC_ACCESS: %d\n", rc);

				return rc;

			}



			rc = qpnp_chg_masked_write(chip,

				chip->buck_base + TEST_EN_SMBC_LOOP,

				IBAT_REGULATION_DISABLE,

				batt_temp_good

				? 0 : IBAT_REGULATION_DISABLE, 1);

			if (rc) {

				pr_err("failed to write COMP_OVR1 rc=%d\n", rc);

				return rc;

			}

			schedule_work(&chip->insertion_ocv_work);

		} else {

			rc = qpnp_chg_masked_write(chip,

				chip->buck_base + SEC_ACCESS,

				0xFF,

				0xA5, 1);

			if (rc) {

				pr_err("failed to write SEC_ACCESS: %d\n", rc);

				return rc;

			}



			rc = qpnp_chg_masked_write(chip,

				chip->buck_base + TEST_EN_SMBC_LOOP,

				IBAT_REGULATION_DISABLE,

				0, 1);

			if (rc) {

				pr_err("failed to write COMP_OVR1 rc=%d\n", rc);

				return rc;

			}

			chip->insertion_ocv_uv = 0;

			qpnp_chg_charge_en(chip, 0);

		}