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Commit e27535b9 authored by Eli Cohen's avatar Eli Cohen Committed by Roland Dreier
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IB/mlx4: Fix memory ordering of VLAN insertion control bits 



We must fully update the control segment before marking it as valid,
so that hardware doesn't start executing it before we're ready.

Signed-off-by: default avatarEli Cohen <eli@mellanox.co.il>

[ Move VLAN control bit setting to before wmb().  - Roland ]

Signed-off-by: default avatarRoland Dreier <rolandd@cisco.com>
parent c48c43e4

drivers/infiniband/hw/mlx4/qp.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -1816,6 +1816,11 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 
		ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?

		ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?

				    MLX4_WQE_CTRL_FENCE : 0) | size;

				    MLX4_WQE_CTRL_FENCE : 0) | size;





		if (be16_to_cpu(vlan) < 0x1000) {

			ctrl->ins_vlan = 1 << 6;

			ctrl->vlan_tag = vlan;

		}



		/*

		/*

		 * Make sure descriptor is fully written before

		 * Make sure descriptor is fully written before

		 * setting ownership bit (because HW can start

		 * setting ownership bit (because HW can start
@@ -1831,11 +1836,6 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 
		ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |

		ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |

			(ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;

			(ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;





		if (be16_to_cpu(vlan) < 0x1000) {

			ctrl->ins_vlan = 1 << 6;

			ctrl->vlan_tag = vlan;

		}



		stamp = ind + qp->sq_spare_wqes;

		stamp = ind + qp->sq_spare_wqes;

		ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);

		ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);