Loading arch/arm/boot/dts/qcom/msmplutonium-iommu.dtsi +16 −16 Original line number Diff line number Diff line Loading @@ -38,8 +38,8 @@ status = "ok"; vdd-supply = <&gdsc_mdss>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>; clocks = <&clock_mmss clk_mdss_axi_clk>, <&clock_mmss clk_mdss_ahb_clk>; clock-names = "core_clk", "iface_clk"; qcom,iommu-pmu-ngroups = <1>; Loading Loading @@ -134,9 +134,9 @@ status = "ok"; vdd-supply = <&gdsc_venus>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; clocks = <&clock_mmss clk_venus0_axi_clk>, <&clock_mmss clk_venus0_ahb_clk>, <&clock_mmss clk_venus0_vcodec0_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; qcom,iommu-bfb-regs = <0x2000 Loading Loading @@ -213,9 +213,10 @@ status = "ok"; vdd-supply = <&gdsc_jpeg>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; qcom,needs-alt-core-clk; clocks = <&clock_mmss clk_camss_jpeg_jpeg_axi_clk>, <&clock_mmss clk_camss_jpeg_jpeg_ahb_clk>, <&clock_mmss clk_camss_top_ahb_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; qcom,iommu-bfb-regs = <0x2000 Loading Loading @@ -262,11 +263,9 @@ vdd-supply = <&gdsc_oxili_cx>; qcom,alt-vdd-supply = <&gdsc_oxili_gx>; qcom,iommu-enable-halt; qcom,needs-alt-core-clk; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; clocks = <&clock_mmss clk_oxili_gfx3d_clk>, <&clock_mmss clk_oxilicx_ahb_clk>; clock-names = "core_clk", "iface_clk"; qcom,iommu-bfb-regs = <0x2000 0x204c Loading Loading @@ -329,9 +328,10 @@ status = "ok"; vdd-supply = <&gdsc_vfe>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; qcom,needs-alt-core-clk; clocks = <&clock_mmss clk_camss_vfe_vfe_axi_clk>, <&clock_mmss clk_camss_vfe_vfe_ahb_clk>, <&clock_mmss clk_camss_top_ahb_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; qcom,iommu-bfb-regs = <0x2000 Loading Loading
arch/arm/boot/dts/qcom/msmplutonium-iommu.dtsi +16 −16 Original line number Diff line number Diff line Loading @@ -38,8 +38,8 @@ status = "ok"; vdd-supply = <&gdsc_mdss>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>; clocks = <&clock_mmss clk_mdss_axi_clk>, <&clock_mmss clk_mdss_ahb_clk>; clock-names = "core_clk", "iface_clk"; qcom,iommu-pmu-ngroups = <1>; Loading Loading @@ -134,9 +134,9 @@ status = "ok"; vdd-supply = <&gdsc_venus>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; clocks = <&clock_mmss clk_venus0_axi_clk>, <&clock_mmss clk_venus0_ahb_clk>, <&clock_mmss clk_venus0_vcodec0_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; qcom,iommu-bfb-regs = <0x2000 Loading Loading @@ -213,9 +213,10 @@ status = "ok"; vdd-supply = <&gdsc_jpeg>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; qcom,needs-alt-core-clk; clocks = <&clock_mmss clk_camss_jpeg_jpeg_axi_clk>, <&clock_mmss clk_camss_jpeg_jpeg_ahb_clk>, <&clock_mmss clk_camss_top_ahb_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; qcom,iommu-bfb-regs = <0x2000 Loading Loading @@ -262,11 +263,9 @@ vdd-supply = <&gdsc_oxili_cx>; qcom,alt-vdd-supply = <&gdsc_oxili_gx>; qcom,iommu-enable-halt; qcom,needs-alt-core-clk; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; clocks = <&clock_mmss clk_oxili_gfx3d_clk>, <&clock_mmss clk_oxilicx_ahb_clk>; clock-names = "core_clk", "iface_clk"; qcom,iommu-bfb-regs = <0x2000 0x204c Loading Loading @@ -329,9 +328,10 @@ status = "ok"; vdd-supply = <&gdsc_vfe>; qcom,iommu-enable-halt; clocks = <&clock_gcc clk_venus0_axi_clk>, <&clock_gcc clk_venus0_ahb_clk>, <&clock_gcc clk_venus0_vcodec0_clk>; qcom,needs-alt-core-clk; clocks = <&clock_mmss clk_camss_vfe_vfe_axi_clk>, <&clock_mmss clk_camss_vfe_vfe_ahb_clk>, <&clock_mmss clk_camss_top_ahb_clk>; clock-names = "core_clk", "iface_clk", "alt_core_clk"; qcom,iommu-bfb-regs = <0x2000 Loading