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Commit e1273708 authored by Subhash Jadavani's avatar Subhash Jadavani
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ARM: dts: msm: add ref clock control register address for MSM8994 



On Qualcomm platforms, there will be many consumers of the source clock
which also supply ref_clk to UFS Device. So even if generic UFS
driver (ufshcd) vote to turn off the source ref_clk, it's very likely that
device ref_clk is still running. Hence some of the qualcomm chipsets have
separate control bit to gate & ungate the UFS ref_clk to device. This
control bit is part of the TLMM register adddress space so it can't be
simulated at clock control bit which means UFS qcom driver has to manually
control this bit to gate or ungate the device ref_clk.
This change adds the UFS ref_clk control register address to UFS PHY node.

Change-Id: I5b68ffee855ff0c6ff3374d8fc9e162e550d1791
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 25b2d8ab

arch/arm/boot/dts/qcom/msm8994.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1047,8 +1047,8 @@ 


	ufsphy1: ufsphy@fc597000 {

			compatible = "qcom,ufs-phy-qmp-20nm";

			reg = <0xfc597000 0xda8>;

			reg-names = "phy_mem";

			reg = <0xfc597000 0xda8>, <0xfd512074 0x4>;

			reg-names = "phy_mem", "dev_ref_clk_ctrl_mem";

			#phy-cells = <0>;

			vdda-phy-supply = <&pm8994_l28>;

			vdda-pll-supply = <&pm8994_l12>;