Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e09df478 authored by Vince Weaver's avatar Vince Weaver Committed by Ingo Molnar
Browse files

perf/x86: Update/fix generic events on P6 PMU 



This patch updates the generic events on p6, including some new
extended cache events.

Values for these events were taken from the equivelant PAPI
predefined events.

Tested on a Pentium II.

Signed-off-by: default avatarVince Weaver <vincent.weaver@maine.edu>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191730080.14552@vincent-weaver-1.um.maine.edu


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 7991c9ca

arch/x86/kernel/cpu/perf_event_p6.c

+104 −7
Original line number Diff line number Diff line
@@ -8,13 +8,106 @@ 
 */

static const u64 p6_perfmon_event_map[] =

{

  [PERF_COUNT_HW_CPU_CYCLES]		= 0x0079,

  [PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

  [PERF_COUNT_HW_CACHE_REFERENCES]	= 0x0f2e,

  [PERF_COUNT_HW_CACHE_MISSES]		= 0x012e,

  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,

  [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,

  [PERF_COUNT_HW_BUS_CYCLES]		= 0x0062,

  [PERF_COUNT_HW_CPU_CYCLES]		= 0x0079,	/* CPU_CLK_UNHALTED */

  [PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,	/* INST_RETIRED     */

  [PERF_COUNT_HW_CACHE_REFERENCES]	= 0x0f2e,	/* L2_RQSTS:M:E:S:I */

  [PERF_COUNT_HW_CACHE_MISSES]		= 0x012e,	/* L2_RQSTS:I       */

  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,	/* BR_INST_RETIRED  */

  [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,	/* BR_MISS_PRED_RETIRED */

  [PERF_COUNT_HW_BUS_CYCLES]		= 0x0062,	/* BUS_DRDY_CLOCKS  */

  [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2,	/* RESOURCE_STALLS  */



};



static __initconst u64 p6_hw_cache_event_ids

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] =

{

 [ C(L1D) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0043,	/* DATA_MEM_REFS       */

                [ C(RESULT_MISS)   ] = 0x0045,	/* DCU_LINES_IN        */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0x0f29,	/* L2_LD:M:E:S:I       */

	},

        [ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

        },

 },

 [ C(L1I ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0080,	/* IFU_IFETCH         */

		[ C(RESULT_MISS)   ] = 0x0f28,	/* L2_IFETCH:M:E:S:I  */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(LL  ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0x0025,	/* L2_M_LINES_INM     */

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(DTLB) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0043,	/* DATA_MEM_REFS      */

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(ITLB) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0080,	/* IFU_IFETCH         */

		[ C(RESULT_MISS)   ] = 0x0085,	/* ITLB_MISS          */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

 },

 [ C(BPU ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x00c4,	/* BR_INST_RETIRED      */

		[ C(RESULT_MISS)   ] = 0x00c5,	/* BR_MISS_PRED_RETIRED */

        },

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

 },

};



static u64 p6_pmu_event_map(int hw_event)
@@ -158,5 +251,9 @@ __init int p6_pmu_init(void) 


	x86_pmu = p6_pmu;



	memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,

		sizeof(hw_cache_event_ids));





	return 0;

}