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Commit e0381e19 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "mmc: sdhci-msm: change the rclk delay value"

parents 6fb8d4ae 665b1c34

drivers/mmc/host/sdhci-msm.c

+10 −9
Original line number Diff line number Diff line
@@ -150,6 +150,8 @@ enum sdc_mpm_pin_state { 


#define CORE_DDR_CONFIG			0x1B8

#define DDR_CONFIG_POR_VAL		0x80040853

#define DDR_CONFIG_PRG_RCLK_DLY_MASK	0x1FF

#define DDR_CONFIG_PRG_RCLK_DLY		115



#define CORE_MCI_DATA_CTRL	0x2C

#define CORE_MCI_DPSM_ENABLE	(1 << 0)
@@ -877,19 +879,18 @@ out: 


static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)

{

	u32 dll_status;

	u32 dll_status, ddr_config;

	int ret = 0;



	pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);



	/*

	 * Currently the CORE_DDR_CONFIG register defaults to desired

	 * configuration on reset. Currently reprogramming the power on

	 * reset (POR) value in case it might have been modified by

	 * bootloaders. In the future, if this changes, then the desired

	 * values will need to be programmed appropriately.

	 * Reprogramming the value in case it might have been modified by

	 * bootloaders.

	 */

	writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);

	ddr_config = DDR_CONFIG_POR_VAL & ~DDR_CONFIG_PRG_RCLK_DLY_MASK;

	ddr_config |= DDR_CONFIG_PRG_RCLK_DLY;

	writel_relaxed(ddr_config, host->ioaddr + CORE_DDR_CONFIG);



	/* Write 1 to DDR_CAL_EN field in CORE_DLL_CONFIG_2 */

	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2)