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Commit dfe218b7 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge commit 'jwb/jwb-next'

parents 34318c25 1ff0fcfc

arch/powerpc/boot/Makefile

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@@ -68,7 +68,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c 
		fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \

		cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \

		cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \

		virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c

		virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \

		cuboot-acadia.c

src-boot := $(src-wlib) $(src-plat) empty.c



src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -211,6 +212,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImage 
# Board ports in arch/powerpc/platform/40x/Kconfig

image-$(CONFIG_EP405)			+= dtbImage.ep405

image-$(CONFIG_WALNUT)			+= treeImage.walnut

image-$(CONFIG_ACADIA)			+= cuImage.acadia



# Board ports in arch/powerpc/platform/44x/Kconfig

image-$(CONFIG_EBONY)			+= treeImage.ebony cuImage.ebony

arch/powerpc/boot/cuboot-acadia.c

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/*

 * Old U-boot compatibility for Acadia

 *

 * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>

 *

 * Copyright 2008 IBM Corporation

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published

 * by the Free Software Foundation.

 */



#include "ops.h"

#include "io.h"

#include "dcr.h"

#include "stdio.h"

#include "4xx.h"

#include "44x.h"

#include "cuboot.h"



#define TARGET_4xx

#include "ppcboot.h"



static bd_t bd;



#define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */



#define PLLC_SRC_MASK	       0x20000000     /* PLL feedback source */



#define PLLD_FBDV_MASK	       0x1F000000     /* PLL feedback divider value */

#define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */

#define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */



#define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */

#define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */

#define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */

#define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */



#define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */

#define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */

#define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */

#define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */



static void get_clocks(void)

{

	unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;

	unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;

	unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;

	unsigned long div;		/* total divisor udiv * bdiv */

	unsigned long umin;		/* minimum udiv	*/

	unsigned short diff;		/* smallest diff */

	unsigned long udiv;		/* best udiv */

	unsigned short idiff;		/* current diff */

	unsigned short ibdiv;		/* current bdiv */

	unsigned long est;		/* current estimate */

	unsigned long baud;

	void *np;



	/* read the sysclk value from the CPLD */

	sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;



	/*

	 * Read PLL Mode registers

	 */

	cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);

	cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);



	/*

	 * Determine forward divider A

	 */

	pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);



	/*

	 * Determine forward divider B

	 */

	pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);

	if (pllFwdDivB == 0)

		pllFwdDivB = 8;



	/*

	 * Determine FBK_DIV.

	 */

	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);

	if (pllFbkDiv == 0)

		pllFbkDiv = 256;



	/*

	 * Read CPR_PRIMAD register

	 */

	cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);



	/*

	 * Determine PLB_DIV.

	 */

	pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);

	if (pllPlbDiv == 0)

		pllPlbDiv = 16;



	/*

	 * Determine EXTBUS_DIV.

	 */

	pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);

	if (pllExtBusDiv == 0)

		pllExtBusDiv = 16;



	/*

	 * Determine OPB_DIV.

	 */

	pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);

	if (pllOpbDiv == 0)

		pllOpbDiv = 16;



	/* There is a bug in U-Boot that prevents us from using

	 * bd.bi_opbfreq because U-Boot doesn't populate it for

	 * 405EZ.  We get to calculate it, yay!

	 */

	freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;



	freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;



	plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?

					   pllFwdDivB : pllFwdDiv) *

		    pllFbkDiv) / pllFwdDivB);



	np = find_node_by_alias("serial0");

	if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))

		fatal("no current-speed property\n\r");



	udiv = 256;			/* Assume lowest possible serial clk */

	div = plloutb / (16 * baud); /* total divisor */

	umin = (plloutb / freqOPB) << 1;	/* 2 x OPB divisor */

	diff = 256;			/* highest possible */



	/* i is the test udiv value -- start with the largest

	 * possible (256) to minimize serial clock and constrain

	 * search to umin.

	 */

	for (i = 256; i > umin; i--) {

		ibdiv = div / i;

		est = i * ibdiv;

		idiff = (est > div) ? (est-div) : (div-est);

		if (idiff == 0) {

			udiv = i;

			break;      /* can't do better */

		} else if (idiff < diff) {

			udiv = i;       /* best so far */

			diff = idiff;   /* update lowest diff*/

		}

	}

	freqUART = plloutb / udiv;



	dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);

	dt_fixup_clock("/plb/ebc", freqEBC);

	dt_fixup_clock("/plb/opb", freqOPB);

	dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);

	dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);

}



static void acadia_fixups(void)

{

	dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);

	get_clocks();

	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);

}

	

void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,

		unsigned long r6, unsigned long r7)

{

	CUBOOT_INIT();

	platform_ops.fixups = acadia_fixups;

	platform_ops.exit = ibm40x_dbcr_reset;

	fdt_init(_dtb_start);

	serial_console_init();

}

arch/powerpc/boot/dts/acadia.dts

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/*

 * Device Tree Source for AMCC Acadia (405EZ)

 *

 * Copyright IBM Corp. 2008

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



/dts-v1/;



/ {

	#address-cells = <1>;

	#size-cells = <1>;

	model = "amcc,acadia";

	compatible = "amcc,acadia";

	dcr-parent = <&{/cpus/cpu@0}>;



	aliases {

		ethernet0 = &EMAC0;

		serial0 = &UART0;

		serial1 = &UART1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			model = "PowerPC,405EZ";

			reg = <0x0>;

			clock-frequency = <0>; /* Filled in by wrapper */

			timebase-frequency = <0>; /* Filled in by wrapper */

			i-cache-line-size = <32>;

			d-cache-line-size = <32>;

			i-cache-size = <16384>;

			d-cache-size = <16384>;

			dcr-controller;

			dcr-access-method = "native";

		};

	};



	memory {

		device_type = "memory";

		reg = <0x0 0x0>; /* Filled in by wrapper */

	};



	UIC0: interrupt-controller {

		compatible = "ibm,uic-405ez", "ibm,uic";

		interrupt-controller;

		dcr-reg = <0x0c0 0x009>;

		cell-index = <0>;

		#address-cells = <0>;

		#size-cells = <0>;

		#interrupt-cells = <2>;

	};



	plb {

		compatible = "ibm,plb-405ez", "ibm,plb3";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		clock-frequency = <0>; /* Filled in by wrapper */



		MAL0: mcmal {

			compatible = "ibm,mcmal-405ez", "ibm,mcmal";

			dcr-reg = <0x380 0x62>;

			num-tx-chans = <1>;

			num-rx-chans = <1>;

			interrupt-parent = <&UIC0>;

			/* 405EZ has only 3 interrupts to the UIC, as

			 * SERR, TXDE, and RXDE are or'd together into

			 * one UIC bit

			 */

			interrupts = <

				0x13 0x4 /* TXEOB */

				0x15 0x4 /* RXEOB */

				0x12 0x4 /* SERR, TXDE, RXDE */>;

		};



		POB0: opb {

			compatible = "ibm,opb-405ez", "ibm,opb";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			dcr-reg = <0x0a 0x05>;

			clock-frequency = <0>; /* Filled in by wrapper */



			UART0: serial@ef600300 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <0xef600300 0x8>;

				virtual-reg = <0xef600300>;

				clock-frequency = <0>; /* Filled in by wrapper */

				current-speed = <115200>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x5 0x4>;

			};



			UART1: serial@ef600400 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <0xef600400 0x8>;

				clock-frequency = <0>; /* Filled in by wrapper */

				current-speed = <115200>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x6 0x4>;

			};



			IIC: i2c@ef600500 {

				compatible = "ibm,iic-405ez", "ibm,iic";

				reg = <0xef600500 0x11>;

				interrupt-parent = <&UIC0>;

				interrupts = <0xa 0x4>;

			};



			GPIO0: gpio@ef600700 {

				compatible = "ibm,gpio-405ez";

				reg = <0xef600700 0x20>;

			};



			GPIO1: gpio@ef600800 {

				compatible = "ibm,gpio-405ez";

				reg = <0xef600800 0x20>;

			};



			EMAC0: ethernet@ef600900 {

				device_type = "network";

				compatible = "ibm,emac-405ez", "ibm,emac";

				interrupt-parent = <&UIC0>;

				interrupts = <

					0x10 0x4 /* Ethernet */

					0x11 0x4 /* Ethernet Wake up */>;

				local-mac-address = [000000000000]; /* Filled in by wrapper */

				reg = <0xef600900 0x70>;

				mal-device = <&MAL0>;

				mal-tx-channel = <0>;

				mal-rx-channel = <0>;

				cell-index = <0>;

				max-frame-size = <1500>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				phy-mode = "mii";

				phy-map = <0x0>;

			};



			CAN0: can@ef601000 {

				compatible = "amcc,can-405ez";

				reg = <0xef601000 0x620>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x7 0x4>;

			};



			CAN1: can@ef601800 {

				compatible = "amcc,can-405ez";

				reg = <0xef601800 0x620>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x8 0x4>;

			};



			cameleon@ef602000 {

				compatible = "amcc,cameleon-405ez";

				reg = <0xef602000 0x800>;

				interrupt-parent = <&UIC0>;

				interrupts = <0xb 0x4 0xc 0x4>;

			};



			ieee1588@ef602800 {

				compatible = "amcc,ieee1588-405ez";

				reg = <0xef602800 0x60>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x4 0x4>;

				/* This thing is a bit weird.  It has it's own UIC

				 * that it uses to generate snapshot triggers.  We

				 * don't really support this device yet, and it needs

				 * work to figure this out.

				 */

				dcr-reg = <0xe0 0x9>;

			};



			usb@ef603000 {

				compatible = "ohci-be";

				reg = <0xef603000 0x80>;

				interrupts-parent = <&UIC0>;

				interrupts = <0xd 0x4 0xe 0x4>;

			};



			dac@ef603300 {

				compatible = "amcc,dac-405ez";

				reg = <0xef603300 0x40>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x18 0x4>;

			};



			adc@ef603400 {

				compatible = "amcc,adc-405ez";

				reg = <0xef603400 0x40>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x17 0x4>;

			};



			spi@ef603500 {

				compatible = "amcc,spi-405ez";

				reg = <0xef603500 0x100>;

				interrupt-parent = <&UIC0>;

				interrupts = <0x9 0x4>;

			};

		};



		EBC0: ebc {

			compatible = "ibm,ebc-405ez", "ibm,ebc";

			dcr-reg = <0x12 0x2>;

			#address-cells = <2>;

			#size-cells = <1>;

			clock-frequency = <0>; /* Filled in by wrapper */

		};

	};



	chosen {

		linux,stdout-path = "/plb/opb/serial@ef600300";

	};

};

arch/powerpc/boot/dts/hcu4.dts

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/*

* Device Tree Source for Netstal Maschinen HCU4

* based on the IBM Walnut

*

* Copyright 2008

* Niklaus Giger <niklaus.giger@member.fsf.org>

*

* Copyright 2007 IBM Corp.

* Josh Boyer <jwboyer@linux.vnet.ibm.com>

*

* This file is licensed under the terms of the GNU General Public

* License version 2.  This program is licensed "as is" without

* any warranty of any kind, whether express or implied.

*/



/dts-v1/;



/ {

	#address-cells = <0x1>;

	#size-cells = <0x1>;

	model = "netstal,hcu4";

	compatible = "netstal,hcu4";

	dcr-parent = <0x1>;



	aliases {

		ethernet0 = "/plb/opb/ethernet@ef600800";

		serial0 = "/plb/opb/serial@ef600300";

	};



	cpus {

		#address-cells = <0x1>;

		#size-cells = <0x0>;



		cpu@0 {

			device_type = "cpu";

			model = "PowerPC,405GPr";

			reg = <0x0>;

			clock-frequency = <0>;		/* Filled in by U-Boot */

			timebase-frequency = <0x0>;	/* Filled in by U-Boot */

			i-cache-line-size = <0x20>;

			d-cache-line-size = <0x20>;

			i-cache-size = <0x4000>;

			d-cache-size = <0x4000>;

			dcr-controller;

			dcr-access-method = "native";

			linux,phandle = <0x1>;

		};

	};



	memory {

		device_type = "memory";

		reg = <0x0 0x0>;	/* Filled in by U-Boot */

	};



	UIC0: interrupt-controller {

		compatible = "ibm,uic";

		interrupt-controller;

		cell-index = <0x0>;

		dcr-reg = <0xc0 0x9>;

		#address-cells = <0x0>;

		#size-cells = <0x0>;

		#interrupt-cells = <0x2>;

		linux,phandle = <0x2>;

	};



	plb {

		compatible = "ibm,plb3";

		#address-cells = <0x1>;

		#size-cells = <0x1>;

		ranges;

		clock-frequency = <0x0>;	/* Filled in by U-Boot */



		SDRAM0: memory-controller {

			compatible = "ibm,sdram-405gp";

			dcr-reg = <0x10 0x2>;

		};



		MAL: mcmal {

			compatible = "ibm,mcmal-405gp", "ibm,mcmal";

			dcr-reg = <0x180 0x62>;

			num-tx-chans = <0x1>;

			num-rx-chans = <0x1>;

			interrupt-parent = <0x2>;

			interrupts = <0xb 0x4 0xc 0x4 0xa 0x4 0xd 0x4 0xe 0x4>;

			linux,phandle = <0x3>;

		};



		POB0: opb {

			compatible = "ibm,opb-405gp", "ibm,opb";

			#address-cells = <0x1>;

			#size-cells = <0x1>;

			ranges = <0xef600000 0xef600000 0xa00000>;

			dcr-reg = <0xa0 0x5>;

			clock-frequency = <0x0>;	/* Filled in by U-Boot */



			UART0: serial@ef600300 {

				device_type = "serial";

				compatible = "ns16550";

				reg = <0xef600300 0x8>;

				virtual-reg = <0xef600300>;

				clock-frequency = <0x0>;/* Filled in by U-Boot */

				current-speed = <0>;	/* Filled in by U-Boot */

				interrupt-parent = <0x2>;

				interrupts = <0x0 0x4>;

			};



			IIC: i2c@ef600500 {

				compatible = "ibm,iic-405gp", "ibm,iic";

				reg = <0xef600500 0x11>;

				interrupt-parent = <0x2>;

				interrupts = <0x2 0x4>;

			};



			GPIO: gpio@ef600700 {

				compatible = "ibm,gpio-405gp";

				reg = <0xef600700 0x20>;

			};



			EMAC: ethernet@ef600800 {

				device_type = "network";

				compatible = "ibm,emac-405gp", "ibm,emac";

				interrupt-parent = <0x2>;

				interrupts = <0xf 0x4 0x9 0x4>;

				local-mac-address = [00 00 00 00 00 00];

				reg = <0xef600800 0x70>;

				mal-device = <0x3>;

				mal-tx-channel = <0x0>;

				mal-rx-channel = <0x0>;

				cell-index = <0x0>;

				max-frame-size = <0x5dc>;

				rx-fifo-size = <0x1000>;

				tx-fifo-size = <0x800>;

				phy-mode = "rmii";

				phy-map = <0x1>;

			};

		};



		EBC0: ebc {

			compatible = "ibm,ebc-405gp", "ibm,ebc";

			dcr-reg = <0x12 0x2>;

			#address-cells = <0x2>;

			#size-cells = <0x1>;

			clock-frequency = <0x0>;	/* Filled in by U-Boot */



			sram@0,0 {

				reg = <0x0 0x0 0x80000>;

			};



			flash@0,80000 {

				compatible = "jedec-flash";

				bank-width = <0x1>;

				reg = <0x0 0x80000 0x80000>;

				#address-cells = <0x1>;

				#size-cells = <0x1>;



				partition@0 {

					label = "OpenBIOS";

					reg = <0x0 0x80000>;

					read-only;

				};

			};

		};

	};



	chosen {

		linux,stdout-path = "/plb/opb/serial@ef600300";

	};

};

arch/powerpc/configs/40x/acadia_defconfig

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