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Commit df2a6a85 authored by Hanumath Prasad's avatar Hanumath Prasad Committed by Anirudh Ghayal
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ARM: msm: dts: Add support for 1.7GHz for MSM8939



Add a new speed bin to identify 1.7GHz. Add additional
cpu frequencies supported. Add the corresponding CCI,
BW and virtual corner mappings.

The Max corner values for each of the client(Perf/power/CCI)
has changed, thus in most of the cases the regulator framework
is unable to find a common max voltage corner to apply and
ends up honoring only the first client. Add dummy Fmax for
Power cluster and CCI to map with max corner of perf cluster
to satisfy the same.

CRs-Fixed: 735037
Change-Id: I11304fc3cfafa0472aeb08b70989c60110bd9116
Signed-off-by: default avatarHanumath Prasad <hpprasad@codeaurora.org>
Signed-off-by: default avatarTirupathi Reddy <tirupath@codeaurora.org>
parent a9eb0283
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+12 −4
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@
		interrupts = <0 15 0>;
		regulator-name = "apc_corner";
		regulator-min-microvolt = <1>;
		regulator-max-microvolt = <20>;
		regulator-max-microvolt = <26>;

		qcom,cpr-fuse-corners = <3>;
		qcom,cpr-voltage-ceiling = <1050000 1150000 1350000>;
@@ -116,7 +116,8 @@
					<27 18 6 0>,
					<27 0 6 0>;
		qcom,cpr-init-voltage-step = <10000>;
		qcom,cpr-corner-map = <1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3>;
		qcom,cpr-corner-map = <1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3
					3 3 3 3 3 3>;
		qcom,cpr-corner-frequency-map =
					<1 200000000>,
					<2 345600000>,
@@ -137,11 +138,18 @@
					<17 1344000000>,
					<18 1420800000>,
					<19 1497600000>,
					<20 1536000000>;
					<20 1536000000>,
					<21 1574400000>,
					<22 1612800000>,
					<23 1632000000>,
					<24 1651200000>,
					<25 1689600000>,
					<26 1708800000>;
		qcom,speed-bin-fuse-sel = <1 34 3 0>;
		qcom,cpr-speed-bin-max-corners =
					<0 0 3 12 17>,
					<2 0 3 12 20>;
					<2 0 3 12 20>,
					<4 0 3 12 26>;
		qcom,cpr-quot-adjust-scaling-factor-max = <900>;
		qcom,cpr-enable;
	};
+62 −3
Original line number Diff line number Diff line
@@ -115,6 +115,44 @@
			<  300000000 12>,
			<  400000000 15>,
			<  600000000 19>;

		qcom,speed4-bin-v0-c0 =
			<          0 0>,
			<  250000000 3>,
			<  500000000 9>,
			<  800000000 12>,
			<  998400000 20>,
			< 1000000000 26>; /*dummy Fmax maps to max corner*/

		qcom,speed4-bin-v0-c1 =
			<          0 0>,
			<  400000000 3>,
			<  800000000 9>,
			<  806400000 10>,
			<  883200000 11>,
			<  960000000 12>,
			< 1036800000 13>,
			< 1113600000 14>,
			< 1190400000 15>,
			< 1267200000 16>,
			< 1344000000 17>,
			< 1420800000 18>,
			< 1497600000 19>,
			< 1536000000 20>,
			< 1574400000 21>,
			< 1612800000 22>,
			< 1632000000 23>,
			< 1651200000 24>,
			< 1689600000 25>,
			< 1708800000 26>;

		qcom,speed4-bin-v0-cci =
			<          0 0>,
			<  200000000 3>,
			<  300000000 12>,
			<  400000000 15>,
			<  600000000 20>,
			<  800000000 26>; /*dummy Fmax maps to max corner*/
		#clock-cells = <1>;
	};

@@ -165,7 +203,14 @@
			<  1267200 6103 >,
			<  1344000 6103 >,
			<  1420800 6103 >,
			<  1497600 6103 >;
			<  1497600 6103 >,
			<  1536000 6103 >,
			<  1574400 6103 >,
			<  1612800 6103 >,
			<  1632000 6103 >,
			<  1651200 6103 >,
			<  1689600 6103 >,
			<  1708800 6103 >;
		cpu-to-dev-map-4 =
			<  200000 1525 >,
			<  249600 2545 >,
@@ -197,7 +242,14 @@
			< 1267200  595200 >,
			< 1344000  595200 >,
			< 1420800  595200 >,
			< 1497600  595200 >;
			< 1497600  595200 >,
			< 1536000  595200 >,
			< 1574400  595200 >,
			< 1612800  595200 >,
			< 1632000  595200 >,
			< 1651200  595200 >,
			< 1689600  595200 >,
			< 1708800  595200 >;
		cpu-to-dev-map-4 =
			<  200000 200000 >,
			<  249600 200000 >,
@@ -245,7 +297,14 @@
			 < 1267200 >,
			 < 1344000 >,
			 < 1420800 >,
			 < 1497600 >;
			 < 1497600 >,
			 < 1536000 >,
			 < 1574400 >,
			 < 1612800 >,
			 < 1632000 >,
			 < 1651200 >,
			 < 1689600 >,
			 < 1708800 >;
		qcom,cpufreq-table-4 =
			 <  200000 >,
			 <  249600 >,
+6 −0
Original line number Diff line number Diff line
@@ -514,6 +514,12 @@ static struct pll_freq_tbl apcs_c1_pll_freq[] = {
	F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1574400000, 82, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1612800000, 84, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1632000000, 85, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1651200000, 86, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1689600000, 88, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),
};

static struct pll_clk a53ss_c1_pll = {