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Commit deb20fb5 authored by Taniya Das's avatar Taniya Das
Browse files

msm: clock-8916: clock changes for 8916



- Update debug_mux select value for gcc_bimc_gpu_clk
to match latest hardware frequency plan.
- Change has_sibling to 0 for gcc_oxili_gfx3d_clk so
that GPU driver can set rate of RCG through this branch
clock.
- Correct the xo_pil_mss_clk which is used by PIL driver
and add it to clock list.
- Add xo_pil_pronto_clk to clock list

Change-Id: I4cb357179a449dfcc5046d35497a843447fa6c67
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 0ff80c12
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+2 −2
Original line number Diff line number Diff line
@@ -2053,7 +2053,7 @@ static struct branch_clk gcc_oxili_ahb_clk = {

static struct branch_clk gcc_oxili_gfx3d_clk = {
	.cbcr_reg = OXILI_GFX3D_CBCR,
	.has_sibling = 1,
	.has_sibling = 0,
	.base = &virt_bases[GCC_BASE],
	.c = {
		.dbg_name = "gcc_oxili_gfx3d_clk",
@@ -2449,7 +2449,7 @@ static struct mux_clk gcc_debug_mux = {
		{&gcc_mdss_vsync_clk.c,			0x01fb},
		{&gcc_mdss_byte0_clk.c,			0x01fc},
		{&gcc_mdss_esc0_clk.c,			0x01fd},
		{&gcc_bimc_gpu_clk.c,			0x015c},
		{&gcc_bimc_gpu_clk.c,			0x0157},
		{&wcnss_m_clk.c,			0x0198},
	),
	.c = {
+3 −2
Original line number Diff line number Diff line
@@ -96,9 +96,8 @@ static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_mss_pil_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
static DEFINE_CLK_BRANCH_VOTER(xo_pil_mba_clk, &xo_clk_src.c);

static struct mux_clk rpm_debug_mux = {
	.ops = &mux_reg_ops,
@@ -129,6 +128,8 @@ static struct clk_lookup msm_clocks_rpm[] = {
	CLK_LIST(xo_a_clk_src),
	CLK_LIST(xo_otg_clk),
	CLK_LIST(xo_lpm_clk),
	CLK_LIST(xo_pil_mss_clk),
	CLK_LIST(xo_pil_pronto_clk),

	CLK_LIST(snoc_msmbus_clk),
	CLK_LIST(snoc_msmbus_a_clk),