Merge "ARM: dts: msm: Reduce SDC1 max clock frequency to 177MHz"

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>;

		clock-names = "iface_clk", "core_clk";

		qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;

		qcom,clk-rates = <400000 25000000 50000000 100000000 177770000>;

		qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";

		status = "disabled";