Loading drivers/crypto/mv_cesa.c +7 −5 Original line number Diff line number Diff line Loading @@ -343,12 +343,14 @@ static void mv_process_hash_current(int first_block) else op.config |= CFG_MID_FRAG; if (first_block) { writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A); writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B); writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C); writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D); writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E); } } memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config)); Loading Loading
drivers/crypto/mv_cesa.c +7 −5 Original line number Diff line number Diff line Loading @@ -343,12 +343,14 @@ static void mv_process_hash_current(int first_block) else op.config |= CFG_MID_FRAG; if (first_block) { writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A); writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B); writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C); writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D); writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E); } } memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config)); Loading