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Commit dc0d51bd authored by Pushkar Joshi's avatar Pushkar Joshi Committed by Gerrit - the friendly Code Review server
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clk: qcom: clock-gcc-8992: Modify gpll4 and sdcc1 clock frequency 



The gpll4 clock is now configured by SBL to run at 1376 MHz. Modify the
frequency for the gpll4 clock and the dependent frequencies for the sdcc1
clock.

Change-Id: I17f2658218ede51e8f10af50a5c413d6be5308c8
Signed-off-by: default avatarPushkar Joshi <pushkarj@codeaurora.org>
parent ce15b0ab

drivers/clk/qcom/clock-gcc-8992.c

+3 −3
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ static struct pll_vote_clk gpll4 = { 
	.status_mask = BIT(30),

	.base = &virt_base,

	.c = {

		.rate = 1536000000,

		.rate = 1376000000,

		.parent = &gcc_xo.c,

		.dbg_name = "gpll4",

		.ops = &clk_ops_pll_vote,
@@ -1102,8 +1102,8 @@ static struct clk_freq_tbl ftbl_sdcc1_apps_clk_src[] = { 
	F(  25000000, gpll0_out_main,   12,    1,     2),

	F(  50000000, gpll0_out_main,   12,    0,     0),

	F( 100000000, gpll0_out_main,    6,    0,     0),

	F( 192000000, gpll4_out_main,    2,    0,     0),

	F( 384000000, gpll4_out_main,    1,    0,     0),

	F( 172000000, gpll4_out_main,    2,    0,     0),

	F( 344000000, gpll4_out_main,    1,    0,     0),

	F_END

};