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Commit d8fb91e8 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Jesper Nilsson
Browse files

CRIS: add pgprot_noncached 



On CRIS, the high address bit controls caching, which means that
we can add a pgprot_noncached() macro that sets this bit in the
address.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarJesper Nilsson <jesper.nilsson@axis.com>
parent adda7661

arch/cris/include/arch-v10/arch/mmu.h

+5 −4
Original line number Diff line number Diff line
@@ -33,10 +33,10 @@ typedef struct 


/* CRIS PTE bits (see R_TLB_LO in the register description)

 *

 *   Bit:  31-13 12-------4    3        2       1       0  

 *         ________________________________________________

 *        | pfn | reserved | global | valid | kernel | we  |

 *        |_____|__________|________|_______|________|_____|

 *   Bit:  31     30-13 12-------4    3        2       1       0

 *         _______________________________________________________

 *        | cache |pfn | reserved | global | valid | kernel | we  |

 *        |_______|____|__________|________|_______|________|_____|

 *

 * (pfn = physical frame number)

 */
@@ -53,6 +53,7 @@ typedef struct 
#define _PAGE_VALID	   (1<<2) /* page is valid */

#define _PAGE_SILENT_READ  (1<<2) /* synonym */

#define _PAGE_GLOBAL       (1<<3) /* global page - context is ignored */

#define _PAGE_NO_CACHE	   (1<<31) /* part of the uncached memory map */



/* Bits the HW doesn't care about but the kernel uses them in SW */

arch/cris/include/arch-v32/arch/mmu.h

+6 −4
Original line number Diff line number Diff line
@@ -28,10 +28,10 @@ typedef struct 
/*

 * CRISv32 PTE bits:

 *

 *  Bit:  31-13  12-5     4        3       2        1        0

 *       +-----+------+--------+-------+--------+-------+---------+

 *       | pfn | zero | global | valid | kernel | write | execute |

 *       +-----+------+--------+-------+--------+-------+---------+

 *  Bit:   31     30-13  12-5     4        3       2        1        0

 *       +-------+-----+------+--------+-------+--------+-------+---------+

 *       | cache | pfn | zero | global | valid | kernel | write | execute |

 *       +-------+-----+------+--------+-------+--------+-------+---------+

 */



/*
@@ -45,6 +45,8 @@ typedef struct 
#define _PAGE_VALID         (1 << 3)	/* Page is valid. */

#define _PAGE_SILENT_READ   (1 << 3)	/* Same as above. */

#define _PAGE_GLOBAL        (1 << 4)	/* Global page. */

#define _PAGE_NO_CACHE	    (1 << 31)	/* part of the uncached memory map */





/*

 * The hardware doesn't care about these bits, but the kernel uses them in

arch/cris/include/asm/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -197,6 +197,8 @@ static inline pte_t __mk_pte(void * page, pgprot_t pgprot) 
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)

{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }



#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))





/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval

 * __pte_page(pte_val) refers to the "virtual" DRAM interval