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Commit d8942054 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Configure BLSP1 UARTDM0 as UART"

parents dde5cd4b db3d705f

arch/arm/boot/dts/qcom/msm8939-pinctrl.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -42,6 +42,30 @@ 
			};

		};



		blsp1_uart1_active {

			qcom,pins = <&gp 0>, <&gp 1>, <&gp 2>, <&gp 3>;

			qcom,num-grp-pins = <4>;

			qcom,pin-func = <2>;

			label = "blsp1_uart1_active";



			hsuart_active: default {

			        drive-strength = <16>;

			        bias-disable;

			};

		};



		blsp1_uart1_sleep {

			qcom,pins = <&gp 0>, <&gp 1>, <&gp 2>, <&gp 3>;

			qcom,num-grp-pins = <4>;

			qcom,pin-func = <0>;

			label = "blsp1_uart1_sleep";



			hsuart_sleep: sleep {

			        drive-strength = <2>;

			        bias-disable;

			};

		};



		sdhc2_cd_pin {

			qcom,pins = <&gp 38>;

			qcom,num-grp-pins = <1>;

arch/arm/boot/dts/qcom/msm8939.dtsi

+30 −10
Original line number Diff line number Diff line
@@ -889,16 +889,6 @@ 
		qcom,android-usb-swfi-latency = <1>;

	};



	blsp1_uart1: serial@78af000 {

		compatible = "qcom,msm-lsuart-v14";

		reg = <0x78af000 0x200>;

		interrupts = <0 107 0>;

		status = "disabled";

		clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,

			 <&clock_gcc clk_gcc_blsp1_ahb_clk>;

		clock-names = "core_clk", "iface_clk";

	};



	blsp1_uart2: serial@78b0000 {

		compatible = "qcom,msm-lsuart-v14";

		reg = <0x78b0000 0x200>;
@@ -1103,6 +1093,36 @@ 
		};

	};



	blsp1_uart1: serial@78af000 {

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78af000 0x200>,

			<0x7884000 0x23000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart1>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 107 0

				1 &intc 0 238 0

				2 &msm_gpio 1 0>;

		qcom,bam-tx-ep-pipe-index = <0>;

		qcom,bam-rx-ep-pipe-index = <1>;

		clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,

			<&clock_gcc clk_gcc_blsp1_ahb_clk>;

		clock-names = "core_clk", "iface_clk";

		qcom,msm-bus,name = "blsp1_uart1";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<86 512 0 0>,

				<86 512 500 800>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&hsuart_active>;

		pinctrl-1 = <&hsuart_sleep>;

	};



	qcom,venus@1de0000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x1de0000 0x4000>;