Loading arch/arm/mach-msm/clock-samarium.c +41 −1 Original line number Diff line number Diff line Loading @@ -183,6 +183,8 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0) #define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760) #define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0) #define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0) #define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8) #define BLSP2_QUP1_I2C_APPS_CMD_RCGR (0x09A0) #define BLSP2_QUP2_I2C_APPS_CMD_RCGR (0x0A20) #define BLSP2_QUP3_I2C_APPS_CMD_RCGR (0x0AA0) Loading Loading @@ -413,6 +415,7 @@ static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo.c); static DEFINE_CLK_BRANCH_VOTER(xo_ehci_host_clk, &xo.c); static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo.c); DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, BB_CLK2_ID); static unsigned int soft_vote_gpll0; Loading Loading @@ -497,6 +500,12 @@ static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = { F_END }; static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { F( 19200000, xo, 1, 0, 0), F( 50000000, gpll0, 12, 0, 0), F_END }; static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR, .set_rate = set_rate_mnd, Loading Loading @@ -595,6 +604,20 @@ static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { }, }; static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = { .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR, .set_rate = set_rate_hid, .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, .current_freq = &rcg_dummy_freq, .base = &virt_bases[GCC_BASE], .c = { .dbg_name = "blsp1_qup6_i2c_apps_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP1(LOW, 50000000), CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c), }, }; static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_4_apps_clk[] = { F( 3686400, gpll0, 1, 96, 15625), F( 7372800, gpll0, 1, 192, 15625), Loading Loading @@ -1143,6 +1166,18 @@ static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { }, }; static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR, .has_sibling = 0, .base = &virt_bases[GCC_BASE], .c = { .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", .parent = &blsp1_qup6_i2c_apps_clk_src.c, .ops = &clk_ops_branch, CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c), }, }; static struct branch_clk gcc_blsp1_uart1_apps_clk = { .cbcr_reg = BLSP1_UART1_APPS_CBCR, .has_sibling = 0, Loading Loading @@ -2944,6 +2979,7 @@ static struct measure_mux_entry measure_mux[] = { {&gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098}, {&gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099}, {&gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a}, {&gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2}, {&gcc_blsp2_ahb_clk.c, GCC_BASE, 0x00a8}, {&gcc_blsp2_qup1_spi_apps_clk.c, GCC_BASE, 0x00aa}, {&gcc_blsp2_qup1_i2c_apps_clk.c, GCC_BASE, 0x00ab}, Loading Loading @@ -3345,7 +3381,8 @@ static struct clk_lookup msm_clocks_samarium[] = { /* measure */ CLK_LOOKUP("measure", measure_clk.c, "debug"), /* NFC */ CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "3-000e"), /* RPM and voter */ CLK_LOOKUP("xo", xo_otg_clk.c, "msm_otg"), CLK_LOOKUP("xo", xo_pil_lpass_clk.c, "fe200000.qcom,lpass"), Loading Loading @@ -3489,6 +3526,9 @@ static struct clk_lookup msm_clocks_samarium[] = { CLK_LOOKUP("", gcc_blsp1_qup3_spi_apps_clk.c, ""), CLK_LOOKUP("", gcc_blsp1_qup4_i2c_apps_clk.c, ""), CLK_LOOKUP("", gcc_blsp1_qup4_spi_apps_clk.c, ""), /* I2C Clocks nfc */ CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9928000.i2c"), CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, "f9928000.i2c"), CLK_LOOKUP("", gcc_blsp1_uart1_apps_clk.c, ""), CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f991e000.serial"), CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"), Loading Loading
arch/arm/mach-msm/clock-samarium.c +41 −1 Original line number Diff line number Diff line Loading @@ -183,6 +183,8 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0) #define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760) #define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0) #define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0) #define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8) #define BLSP2_QUP1_I2C_APPS_CMD_RCGR (0x09A0) #define BLSP2_QUP2_I2C_APPS_CMD_RCGR (0x0A20) #define BLSP2_QUP3_I2C_APPS_CMD_RCGR (0x0AA0) Loading Loading @@ -413,6 +415,7 @@ static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo.c); static DEFINE_CLK_BRANCH_VOTER(xo_ehci_host_clk, &xo.c); static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo.c); DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, BB_CLK2_ID); static unsigned int soft_vote_gpll0; Loading Loading @@ -497,6 +500,12 @@ static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = { F_END }; static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { F( 19200000, xo, 1, 0, 0), F( 50000000, gpll0, 12, 0, 0), F_END }; static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR, .set_rate = set_rate_mnd, Loading Loading @@ -595,6 +604,20 @@ static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { }, }; static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = { .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR, .set_rate = set_rate_hid, .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, .current_freq = &rcg_dummy_freq, .base = &virt_bases[GCC_BASE], .c = { .dbg_name = "blsp1_qup6_i2c_apps_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP1(LOW, 50000000), CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c), }, }; static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_4_apps_clk[] = { F( 3686400, gpll0, 1, 96, 15625), F( 7372800, gpll0, 1, 192, 15625), Loading Loading @@ -1143,6 +1166,18 @@ static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { }, }; static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR, .has_sibling = 0, .base = &virt_bases[GCC_BASE], .c = { .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", .parent = &blsp1_qup6_i2c_apps_clk_src.c, .ops = &clk_ops_branch, CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c), }, }; static struct branch_clk gcc_blsp1_uart1_apps_clk = { .cbcr_reg = BLSP1_UART1_APPS_CBCR, .has_sibling = 0, Loading Loading @@ -2944,6 +2979,7 @@ static struct measure_mux_entry measure_mux[] = { {&gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098}, {&gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099}, {&gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a}, {&gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2}, {&gcc_blsp2_ahb_clk.c, GCC_BASE, 0x00a8}, {&gcc_blsp2_qup1_spi_apps_clk.c, GCC_BASE, 0x00aa}, {&gcc_blsp2_qup1_i2c_apps_clk.c, GCC_BASE, 0x00ab}, Loading Loading @@ -3345,7 +3381,8 @@ static struct clk_lookup msm_clocks_samarium[] = { /* measure */ CLK_LOOKUP("measure", measure_clk.c, "debug"), /* NFC */ CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "3-000e"), /* RPM and voter */ CLK_LOOKUP("xo", xo_otg_clk.c, "msm_otg"), CLK_LOOKUP("xo", xo_pil_lpass_clk.c, "fe200000.qcom,lpass"), Loading Loading @@ -3489,6 +3526,9 @@ static struct clk_lookup msm_clocks_samarium[] = { CLK_LOOKUP("", gcc_blsp1_qup3_spi_apps_clk.c, ""), CLK_LOOKUP("", gcc_blsp1_qup4_i2c_apps_clk.c, ""), CLK_LOOKUP("", gcc_blsp1_qup4_spi_apps_clk.c, ""), /* I2C Clocks nfc */ CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9928000.i2c"), CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, "f9928000.i2c"), CLK_LOOKUP("", gcc_blsp1_uart1_apps_clk.c, ""), CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f991e000.serial"), CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"), Loading