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Commit d6d04435 authored by Hanumath Prasad's avatar Hanumath Prasad
Browse files

ARM: dts: msm: Add a CPU clock scaling device 



Add a device node that will allow scaling of the clusters
on the MSM8939 and MSM8936 SOC.

Change-Id: Iec3ff3eac8b0335f12247ab7af7d6e3b65444c7e
Signed-off-by: default avatarHanumath Prasad <hpprasad@codeaurora.org>
parent feb2a226

arch/arm/boot/dts/qcom/msm8936.dtsi

+52 −0
Original line number Diff line number Diff line
@@ -24,3 +24,55 @@ 
	qcom,msm-id = <233 0>;

};



&soc {

	clock_cpu: qcom,cpu-clock-8936@b011050 {

		compatible = "qcom,cpu-clock-8936";

		reg = <0xb011050 0x8>,

			<0xb1d1050 0x8>;

		reg-names = "apcs-c1-rcg-base",

				"apcs-cci-rcg-base";

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_c1_pll>,

			 <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_cci_pll>;

		clock-names = "clk-c1-4", "clk-c1-5",

				"clk-cci-4", "clk-cci-5";

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  400000000 1>,

			<  800000000 2>,

			< 1536800000 3>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  200000000 1>,

			<  300000000 2>,

			<  800000000 3>;

		#clock-cells = <1>;

	};



	qcom,msm-cpufreq {

		compatible = "qcom,msm-cpufreq";

		clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk",

				"cpu3_clk";

		clocks = <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>;



		qcom,cpufreq-table-0 =

			 <  200000 >,

			 <  345600 >,

			 <  400000 >,

			 <  422400 >,

			 <  499200 >,

			 <  533330 >,

			 <  652800 >,

			 <  800000 >,

			 < 1113600 >,

			 < 1267200 >,

			 < 1344000 >;

	};

};

arch/arm/boot/dts/qcom/msm8939-common.dtsi

+0 −76
Original line number Diff line number Diff line
@@ -595,82 +595,6 @@ 
		#clock-cells = <1>;

	};



	clock_cpu: qcom,cpu-clock-8939@b111050 {

		compatible = "qcom,cpu-clock-8939";

		reg = <0x0b111050 0x8>,

			<0xb011050 0x8>,

			<0xb1d1050 0x8>;

		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",

				"apcs-cci-rcg-base";

		vdd-c0-supply = <&apc_vreg_corner>;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_c0_pll>,

			 <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_c1_pll>,

			 <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_cci_pll>;

		clock-names = "clk-c0-4", "clk-c0-5",

				"clk-c1-4", "clk-c1-5",

				"clk-cci-4", "clk-cci-5";

		qcom,speed0-bin-v0-c0 =

			<          0 0>,

			<  250000000 1>,

			<  500000000 2>,

			<  998400000 3>;



		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  400000000 1>,

			<  800000000 2>,

			< 1536800000 3>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  200000000 1>,

			<  300000000 2>,

			<  800000000 3>;

		#clock-cells = <1>;

	};



	qcom,msm-cpufreq {

		compatible = "qcom,msm-cpufreq";

		clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk",

				"cpu3_clk", "cpu4_clk", "cpu5_clk",

				"cpu6_clk", "cpu7_clk";

		clocks = <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>;



		qcom,governor-per-policy;



		qcom,cpufreq-table-0 =

			 <  200000 >,

			 <  345600 >,

			 <  400000 >,

			 <  422400 >,

			 <  499200 >,

			 <  533330 >,

			 <  652800 >,

			 <  800000 >,

			 < 1113600 >,

			 < 1267200 >,

			 < 1344000 >;

		qcom,cpufreq-table-4 =

			 <  200000 >,

			 <  249600 >,

                         <  400000 >,

                         <  499200 >,

                         <  800000 >,

                         <  998400 >;

	};



	qcom_tzlog: tz-log@8600720 {

		compatible = "qcom,tz-log";

		reg = <0x08600720 0x1000>;

arch/arm/boot/dts/qcom/msm8939.dtsi

+77 −0
Original line number Diff line number Diff line
@@ -25,3 +25,80 @@ 
	qcom,msm-id = <239 0>, <241 0>;

};



&soc {

	clock_cpu: qcom,cpu-clock-8939@b111050 {

		compatible = "qcom,cpu-clock-8939";

		reg = <0x0b111050 0x8>,

			<0xb011050 0x8>,

			<0xb1d1050 0x8>;

		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",

				"apcs-cci-rcg-base";

		vdd-c0-supply = <&apc_vreg_corner>;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_c0_pll>,

			 <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_c1_pll>,

			 <&clock_gcc clk_gpll0_ao>,

			 <&clock_gcc clk_a53ss_cci_pll>;

		clock-names = "clk-c0-4", "clk-c0-5",

				"clk-c1-4", "clk-c1-5",

				"clk-cci-4", "clk-cci-5";

		qcom,speed0-bin-v0-c0 =

			<          0 0>,

			<  250000000 1>,

			<  500000000 2>,

			<  998400000 3>;



		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  400000000 1>,

			<  800000000 2>,

			< 1536800000 3>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  200000000 1>,

			<  300000000 2>,

			<  800000000 3>;

		#clock-cells = <1>;

	};



	qcom,msm-cpufreq {

		compatible = "qcom,msm-cpufreq";

		clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk",

				"cpu3_clk", "cpu4_clk", "cpu5_clk",

				"cpu6_clk", "cpu7_clk";

		clocks = <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>;



		qcom,governor-per-policy;



		qcom,cpufreq-table-0 =

			 <  200000 >,

			 <  345600 >,

			 <  400000 >,

			 <  422400 >,

			 <  499200 >,

			 <  533330 >,

			 <  652800 >,

			 <  800000 >,

			 < 1113600 >,

			 < 1267200 >,

			 < 1344000 >;

		qcom,cpufreq-table-4 =

			 <  200000 >,

			 <  249600 >,

			 <  400000 >,

			 <  499200 >,

			 <  800000 >,

			 <  998400 >;

	};

};