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Commit d6ccda18 authored by Arun KS's avatar Arun KS
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ARM: dts: msm: Enable CPU scaling support for msmtellurium 



We have two clusters and they support different frequencies.
Use separate frequency table for both.

Tellurium cpu clock tree matches with 8939. Hence reuse 8939
driver.

Also document the compatible string.

Change-Id: Ic0e32c73072820db01404d6766d889b30107ca6d
Signed-off-by: default avatarArun KS <arunks@codeaurora.org>
parent 57104a38

Documentation/devicetree/bindings/arm/msm/clock-cpu-8939.txt

0 → 100644
+72 −0
Original line number Diff line number Diff line 
Qualcomm MSM8939 CPU clock tree



clock-cpu-8939 is a device that represents the MSM8939 or MSMTellurium CPU

subsystem clock tree. It lists the various power supplies that need to be

scaled when the clocks are scaled and also other HW specific parameters like

fmax tables, avs settings table, etc.



Required properties:

- compatible:		Must be one of "qcom,clock-cpu-8939" or

			"qcom,cpu-clock-tellurium"

- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Expected

			bases are:

			"apcs-c0-rcg-base", "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "efuse"

- vdd-c0-supply:	The regulator powering the little cluster

- vdd-c1-supply:	The regulator powering the big cluster

- vdd-cci-supply:	The regulator powering the CCI cluster

- qcom,speedX-bin-vY-ZZZ:

			A table of CPU frequency (Hz) to voltage (corner)

			mapping that represents the max frequency possible

			for each supported voltage level for a CPU. 'X' is

			the speed bin into which the device falls into - a

			bin will have unique frequency-voltage relationships.

			'Y' is the characterization version, implying that

			characterization (deciding what speed bin a device

			falls into) methods and/or encoding may change. The

			values 'X' and 'Y' are read from efuse registers, and

			the right table is picked from multiple possible tables.

			'ZZZ' can be c1, c0 or cci depending on whether the table

			is for the big cluster, little cluster or cci.

Example:

	clock_cpu: qcom,cpu-clock-8939@f9015000 {

		compatible = "qcom,cpu-clock-8939";

		reg = <0xf9015000 0x1000>,

		      <0xf9016000 0x1000>,

		      <0xf9011000 0x1000>,

		      <0xf900d000 0x1000>,

		      <0xf900f000 0x1000>,

		      <0xf9112000 0x1000>;

		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",

			     "apcs-cci-rcg-base", "efuse";

                vdd-c0-supply = <&apc_vreg_corner>;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		qcom,speed0-bin-v0-c0 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1286400000 3>;

		qcom,speed0-bin-v0-c1 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1785600000 3>;

		qcom,speed0-bin-v0-cci =

			<         0 0>,

			< 150000000 1>,

			< 300000000 2>,

			< 600000000 3>;

		clocks = <&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_c0_pll>,

			<&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_c1_pll>,

			<&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_cci_pll>;

			clock-names = "clk-c0-4", "clk-c0-5",

			"clk-c1-4", "clk-c1-5",

			"clk-cci-4", "clk-cci-5";

		#clock-cells = <1>;

};

arch/arm/boot/dts/qcom/msmtellurium.dtsi

+73 −0
Original line number Diff line number Diff line
@@ -142,6 +142,45 @@ 
		#clock-cells = <1>;

	};



	clock_cpu: qcom,cpu-clock-8939@b111050 {

		compatible = "qcom,cpu-clock-8939";

		reg =   <0xb111050 0x8>,

			<0xb011050 0x8>,

			<0xb1d1050 0x8>;

		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",

				"apcs-cci-rcg-base";

		vdd-c0-supply = <&apc_vreg_corner>;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_gpll0_ao_clk_src>,

			 <&clock_gcc clk_a53ss_c0_pll>,

			 <&clock_gcc clk_gpll0_ao_clk_src>,

			 <&clock_gcc clk_a53ss_c1_pll>,

			 <&clock_gcc clk_gpll0_ao_clk_src>,

			 <&clock_gcc clk_a53ss_cci_pll>;

		clock-names = "clk-c0-4", "clk-c0-5",

				"clk-c1-4", "clk-c1-5",

				"clk-cci-4", "clk-cci-5";

		qcom,speed0-bin-v0-c0 =

			<          0 0>,

			<  249600000 1>,

			<  499200000 2>,

			<  998400000 3>;



		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  400000000 1>,

			<  800000000 2>,

			< 1536000000 3>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  230400000 1>,

			<  460800000 2>,

			<  595200000 3>;

		#clock-cells = <1>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <1 2 0xff08>,
@@ -151,6 +190,40 @@ 
		clock-frequency = <19200000>;

	};



	qcom,msm-cpufreq {

		compatible = "qcom,msm-cpufreq";

		clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",

				"cpu3_clk", "cpu4_clk", "cpu5_clk",

				"cpu6_clk", "cpu7_clk";

		clocks = <&clock_cpu clk_a53ssmux_cci>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>;



		qcom,cpufreq-table-0 =

			 <  200000 >,

			 <  345600 >,

			 <  400000 >,

			 <  533330 >,

			 <  800000 >,

                         <  960000 >,

			 < 1113600 >,

			 < 1344000 >,

			 < 1497600 >,

			 < 1536000 >;

		qcom,cpufreq-table-4 =

			 <  200000 >,

			 <  249600 >,

			 <  499200 >,

			 <  800000 >,

			 <  998400 >;

	};



	timer@b120000 {

		#address-cells = <1>;

		#size-cells = <1>;