Loading drivers/net/ethernet/msm/emac/emac.h +1 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ struct emac_hw { enum emac_dma_order dma_order; /* PHY parameter */ u32 phy_addr; u16 phy_id[2]; u32 autoneg_advertised; u32 link_speed; Loading drivers/net/ethernet/msm/emac/emac_defines.h +1 −0 Original line number Diff line number Diff line Loading @@ -38,6 +38,7 @@ /* EMAC_PHY_STS */ #define PHY_ADDR_BMSK 0x1f0000 #define PHY_ADDR_SHFT 16 /* EMAC_MDIO_EX_CTRL */ #define DEVAD_BMSK 0x1f0000 Loading drivers/net/ethernet/msm/emac/emac_hw.c +10 −6 Original line number Diff line number Diff line Loading @@ -67,8 +67,9 @@ int emac_hw_read_phy_reg(struct emac_hw *hw, bool ext, u8 dev, bool fast, clk_sel = fast ? MDIO_CLK_25_4 : MDIO_CLK_25_28; emac_reg_update32(hw, EMAC, EMAC_MDIO_CTRL, MDIO_AP_EN, 0); emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, 0); wmb(); /* ensure PHY address is cleared before we proceed */ emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, (dev << PHY_ADDR_SHFT)); wmb(); /* ensure PHY address is set before we proceed */ udelay(1000); if (ext) { Loading Loading @@ -119,8 +120,9 @@ int emac_hw_write_phy_reg(struct emac_hw *hw, bool ext, u8 dev, clk_sel = fast ? MDIO_CLK_25_4 : MDIO_CLK_25_28; emac_reg_update32(hw, EMAC, EMAC_MDIO_CTRL, MDIO_AP_EN, 0); emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, 0); wmb(); /* ensure PHY address is cleared before we proceed */ emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, (dev << PHY_ADDR_SHFT)); wmb(); /* ensure PHY address is set before we proceed */ udelay(1000); if (ext) { Loading Loading @@ -167,7 +169,8 @@ int emac_read_phy_reg(struct emac_hw *hw, u16 reg_addr, u16 *phy_data) int retval; spin_lock_irqsave(&hw->mdio_lock, flags); retval = emac_hw_read_phy_reg(hw, false, 0, true, reg_addr, phy_data); retval = emac_hw_read_phy_reg(hw, false, hw->phy_addr, true, reg_addr, phy_data); spin_unlock_irqrestore(&hw->mdio_lock, flags); if (retval) Loading @@ -185,7 +188,8 @@ int emac_write_phy_reg(struct emac_hw *hw, u16 reg_addr, u16 phy_data) int retval; spin_lock_irqsave(&hw->mdio_lock, flags); retval = emac_hw_write_phy_reg(hw, false, 0, true, reg_addr, phy_data); retval = emac_hw_write_phy_reg(hw, false, hw->phy_addr, true, reg_addr, phy_data); spin_unlock_irqrestore(&hw->mdio_lock, flags); if (retval) Loading drivers/net/ethernet/msm/emac/emac_main.c +1 −0 Original line number Diff line number Diff line Loading @@ -2187,6 +2187,7 @@ static int emac_probe(struct platform_device *pdev) adpt->irq_info[i].rxque = &adpt->rx_queue[i]; } hw->phy_addr = 0; adpt->tstamp_en = true; retval = emac_get_resources(pdev, adpt); if (retval) Loading Loading
drivers/net/ethernet/msm/emac/emac.h +1 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ struct emac_hw { enum emac_dma_order dma_order; /* PHY parameter */ u32 phy_addr; u16 phy_id[2]; u32 autoneg_advertised; u32 link_speed; Loading
drivers/net/ethernet/msm/emac/emac_defines.h +1 −0 Original line number Diff line number Diff line Loading @@ -38,6 +38,7 @@ /* EMAC_PHY_STS */ #define PHY_ADDR_BMSK 0x1f0000 #define PHY_ADDR_SHFT 16 /* EMAC_MDIO_EX_CTRL */ #define DEVAD_BMSK 0x1f0000 Loading
drivers/net/ethernet/msm/emac/emac_hw.c +10 −6 Original line number Diff line number Diff line Loading @@ -67,8 +67,9 @@ int emac_hw_read_phy_reg(struct emac_hw *hw, bool ext, u8 dev, bool fast, clk_sel = fast ? MDIO_CLK_25_4 : MDIO_CLK_25_28; emac_reg_update32(hw, EMAC, EMAC_MDIO_CTRL, MDIO_AP_EN, 0); emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, 0); wmb(); /* ensure PHY address is cleared before we proceed */ emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, (dev << PHY_ADDR_SHFT)); wmb(); /* ensure PHY address is set before we proceed */ udelay(1000); if (ext) { Loading Loading @@ -119,8 +120,9 @@ int emac_hw_write_phy_reg(struct emac_hw *hw, bool ext, u8 dev, clk_sel = fast ? MDIO_CLK_25_4 : MDIO_CLK_25_28; emac_reg_update32(hw, EMAC, EMAC_MDIO_CTRL, MDIO_AP_EN, 0); emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, 0); wmb(); /* ensure PHY address is cleared before we proceed */ emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK, (dev << PHY_ADDR_SHFT)); wmb(); /* ensure PHY address is set before we proceed */ udelay(1000); if (ext) { Loading Loading @@ -167,7 +169,8 @@ int emac_read_phy_reg(struct emac_hw *hw, u16 reg_addr, u16 *phy_data) int retval; spin_lock_irqsave(&hw->mdio_lock, flags); retval = emac_hw_read_phy_reg(hw, false, 0, true, reg_addr, phy_data); retval = emac_hw_read_phy_reg(hw, false, hw->phy_addr, true, reg_addr, phy_data); spin_unlock_irqrestore(&hw->mdio_lock, flags); if (retval) Loading @@ -185,7 +188,8 @@ int emac_write_phy_reg(struct emac_hw *hw, u16 reg_addr, u16 phy_data) int retval; spin_lock_irqsave(&hw->mdio_lock, flags); retval = emac_hw_write_phy_reg(hw, false, 0, true, reg_addr, phy_data); retval = emac_hw_write_phy_reg(hw, false, hw->phy_addr, true, reg_addr, phy_data); spin_unlock_irqrestore(&hw->mdio_lock, flags); if (retval) Loading
drivers/net/ethernet/msm/emac/emac_main.c +1 −0 Original line number Diff line number Diff line Loading @@ -2187,6 +2187,7 @@ static int emac_probe(struct platform_device *pdev) adpt->irq_info[i].rxque = &adpt->rx_queue[i]; } hw->phy_addr = 0; adpt->tstamp_en = true; retval = emac_get_resources(pdev, adpt); if (retval) Loading