Merge "msm: kgsl: Add support for A310 GPU" (d4ab71ec) · Commits · e / devices / android_kernel_sony_msm8994

drivers/gpu/msm/a3xx_reg.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -761,6 +761,7 @@
		/* RBBM_CLOCK_CTL default value */
		#define A305_RBBM_CLOCK_CTL_DEFAULT 0xAAAAAAAA
		#define A305C_RBBM_CLOCK_CTL_DEFAULT 0xAAAAAAAA
		#define A310_RBBM_CLOCK_CTL_DEFAULT 0xAAAAAAAA
		#define A320_RBBM_CLOCK_CTL_DEFAULT 0xBFFFFFFF
		#define A330_RBBM_CLOCK_CTL_DEFAULT 0xBFFCFFFF
		#define A330v2_RBBM_CLOCK_CTL_DEFAULT 0xAAAAAAAA
		@@ -768,6 +769,7 @@

		#define A330_RBBM_GPR0_CTL_DEFAULT 0x00000000
		#define A330v2_RBBM_GPR0_CTL_DEFAULT 0x05515455
		#define A310_RBBM_GPR0_CTL_DEFAULT 0x000000AA

		/* COUNTABLE FOR SP PERFCOUNTER */
		#define SP_FS_FULL_ALU_INSTRUCTIONS 0x0E

drivers/gpu/msm/adreno.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -214,6 +214,10 @@ static const struct {
		{ ADRENO_REV_A420, 4, 2, 0, ANY_ID,
		"a420_pm4.fw", "a420_pfp.fw", &adreno_a4xx_gpudev,
		512, 0, 2, (SZ_1M + SZ_512K), NO_VER, NO_VER },
		{ ADRENO_REV_A310, 3, 1, 0, 0x10,
		"a330_pm4.fw", "a330_pfp.fw", &adreno_a3xx_gpudev,
		512, 0, 2, SZ_512K, NO_VER, NO_VER, 0x8AD, 0x2E4, 0x201,
		0x200 },
		};

		/**
		@@ -1525,6 +1529,7 @@ adreno_ocmem_gmem_malloc(struct adreno_device *adreno_dev)
		{
		if (!(adreno_is_a330(adreno_dev) \|\|
		adreno_is_a305b(adreno_dev) \|\|
		adreno_is_a310(adreno_dev) \|\|
		adreno_is_a4xx(adreno_dev)))
		return 0;

		@@ -1548,6 +1553,7 @@ adreno_ocmem_gmem_free(struct adreno_device *adreno_dev)
		{
		if (!(adreno_is_a330(adreno_dev) \|\|
		adreno_is_a305b(adreno_dev) \|\|
		adreno_is_a310(adreno_dev) \|\|
		adreno_is_a4xx(adreno_dev)))
		return;

drivers/gpu/msm/adreno.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -82,6 +82,7 @@ enum adreno_gpurev {
		ADRENO_REV_A225 = 225,
		ADRENO_REV_A305 = 305,
		ADRENO_REV_A305C = 306,
		ADRENO_REV_A310 = 310,
		ADRENO_REV_A320 = 320,
		ADRENO_REV_A330 = 330,
		ADRENO_REV_A305B = 335,
		@@ -582,6 +583,11 @@ static inline int adreno_is_a305c(struct adreno_device *adreno_dev)
		return (adreno_dev->gpurev == ADRENO_REV_A305C);
		}

		static inline int adreno_is_a310(struct adreno_device *adreno_dev)
		{
		return (adreno_dev->gpurev == ADRENO_REV_A310);
		}

		static inline int adreno_is_a320(struct adreno_device *adreno_dev)
		{
		return (adreno_dev->gpurev == ADRENO_REV_A320);

drivers/gpu/msm/adreno_a3xx.c

+17 −1

Original line number	Diff line number	Diff line
		@@ -452,6 +452,8 @@ unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device
		return A305_RBBM_CLOCK_CTL_DEFAULT;
		else if (adreno_is_a305c(adreno_dev))
		return A305C_RBBM_CLOCK_CTL_DEFAULT;
		else if (adreno_is_a310(adreno_dev))
		return A310_RBBM_CLOCK_CTL_DEFAULT;
		else if (adreno_is_a320(adreno_dev))
		return A320_RBBM_CLOCK_CTL_DEFAULT;
		else if (adreno_is_a330v2(adreno_dev))
		@@ -3601,6 +3603,16 @@ static const struct adreno_vbif_data a305c_vbif[] = {
		{0, 0},
		};

		static const struct adreno_vbif_data a310_vbif[] = {
		{ A3XX_VBIF_ABIT_SORT, 0x0001000F },
		{ A3XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
		/* Enable WR-REQ */
		{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001 },
		/* Set up VBIF_ROUND_ROBIN_QOS_ARB */
		{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x3 },
		{0, 0},
		};

		static const struct adreno_vbif_data a320_vbif[] = {
		/* Set up 16 deep read/write request queues */
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010 },
		@@ -3670,6 +3682,7 @@ static const struct adreno_vbif_data a330v2_vbif[] = {
		const struct adreno_vbif_platform a3xx_vbif_platforms[] = {
		{ adreno_is_a305, a305_vbif },
		{ adreno_is_a305c, a305c_vbif },
		{ adreno_is_a310, a310_vbif },
		{ adreno_is_a320, a320_vbif },
		/* A330v2 needs to be ahead of A330 so the right device matches */
		{ adreno_is_a330v2, a330v2_vbif },
		@@ -4002,10 +4015,13 @@ static void a3xx_start(struct adreno_device *adreno_dev)
		else if (adreno_is_a330(adreno_dev))
		kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
		A330_RBBM_GPR0_CTL_DEFAULT);
		else if (adreno_is_a310(adreno_dev))
		kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
		A310_RBBM_GPR0_CTL_DEFAULT);

		/* Set the OCMEM base address for A330 */
		if (adreno_is_a330(adreno_dev) \|\|
		adreno_is_a305b(adreno_dev)) {
		adreno_is_a305b(adreno_dev) \|\| adreno_is_a310(adreno_dev)) {
		kgsl_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
		(unsigned int)(adreno_dev->ocmem_base >> 14));
		}

drivers/gpu/msm/adreno_ringbuffer.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -391,7 +391,8 @@ int _ringbuffer_start_common(struct adreno_ringbuffer *rb)
		if (adreno_is_a305(adreno_dev) \|\| adreno_is_a305c(adreno_dev) \|\|
		adreno_is_a320(adreno_dev))
		kgsl_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000E0602);
		else if (adreno_is_a330(adreno_dev) \|\| adreno_is_a305b(adreno_dev))
		else if (adreno_is_a330(adreno_dev) \|\| adreno_is_a305b(adreno_dev) \|\|
		adreno_is_a310(adreno_dev))
		kgsl_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x003E2008);

		rb->wptr = 0;