Loading drivers/usb/dwc3/dwc3-msm.c +13 −0 Original line number Diff line number Diff line Loading @@ -202,6 +202,7 @@ struct dwc3_msm { #define MDWC3_PHY_REF_AND_CORECLK_OFF \ (MDWC3_PHY_REF_CLK_OFF | MDWC3_CORECLK_OFF) u32 gctl_val; u32 qscratch_ctl_val; dev_t ext_chg_dev; struct cdev ext_chg_cdev; Loading Loading @@ -1144,6 +1145,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned event) dwc->tx_fifo_size = mdwc->tx_fifo_size; break; case DWC3_CONTROLLER_POST_INITIALIZATION_EVENT: /* * Workaround: Disable internal clock gating always, as there * is a known HW bug that causes the internal RAM clock to get * stuck when entering low power modes. */ dwc3_msm_write_reg_field(mdwc->base, DWC3_GCTL, DWC3_GCTL_DSBLCLKGTNG, 1); usb_phy_post_init(mdwc->ss_phy); break; case DWC3_CONTROLLER_CONNDONE_EVENT: Loading Loading @@ -1702,6 +1710,9 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc) /* make sure above writes are completed before turning off clocks */ wmb(); /* Save value of GCTL to rewrite upon resume */ mdwc->gctl_val = dwc3_msm_read_reg(mdwc->base, DWC3_GCTL); /* Perform controller power collapse */ if (!host_bus_suspend && mdwc->power_collapse && !cable_connected) { mdwc->lpm_flags |= MDWC3_POWER_COLLAPSE; Loading Loading @@ -1858,6 +1869,8 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) mdwc->lpm_flags &= ~MDWC3_POWER_COLLAPSE; } dwc3_msm_write_reg(mdwc->base, DWC3_GCTL, mdwc->gctl_val); atomic_set(&dwc->in_lpm, 0); msm_bam_notify_lpm_resume(DWC3_CTRL); Loading Loading
drivers/usb/dwc3/dwc3-msm.c +13 −0 Original line number Diff line number Diff line Loading @@ -202,6 +202,7 @@ struct dwc3_msm { #define MDWC3_PHY_REF_AND_CORECLK_OFF \ (MDWC3_PHY_REF_CLK_OFF | MDWC3_CORECLK_OFF) u32 gctl_val; u32 qscratch_ctl_val; dev_t ext_chg_dev; struct cdev ext_chg_cdev; Loading Loading @@ -1144,6 +1145,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned event) dwc->tx_fifo_size = mdwc->tx_fifo_size; break; case DWC3_CONTROLLER_POST_INITIALIZATION_EVENT: /* * Workaround: Disable internal clock gating always, as there * is a known HW bug that causes the internal RAM clock to get * stuck when entering low power modes. */ dwc3_msm_write_reg_field(mdwc->base, DWC3_GCTL, DWC3_GCTL_DSBLCLKGTNG, 1); usb_phy_post_init(mdwc->ss_phy); break; case DWC3_CONTROLLER_CONNDONE_EVENT: Loading Loading @@ -1702,6 +1710,9 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc) /* make sure above writes are completed before turning off clocks */ wmb(); /* Save value of GCTL to rewrite upon resume */ mdwc->gctl_val = dwc3_msm_read_reg(mdwc->base, DWC3_GCTL); /* Perform controller power collapse */ if (!host_bus_suspend && mdwc->power_collapse && !cable_connected) { mdwc->lpm_flags |= MDWC3_POWER_COLLAPSE; Loading Loading @@ -1858,6 +1869,8 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) mdwc->lpm_flags &= ~MDWC3_POWER_COLLAPSE; } dwc3_msm_write_reg(mdwc->base, DWC3_GCTL, mdwc->gctl_val); atomic_set(&dwc->in_lpm, 0); msm_bam_notify_lpm_resume(DWC3_CTRL); Loading