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Commit d4019006 authored by Kevin Matlage's avatar Kevin Matlage Committed by Jordan Crouse
Browse files

msm: kgsl: Return HI offset from kgsl_perfcounter_get 



Previously, kgsl_perfcounter_get only returned the offset
of the LO perf counter register. This assumed that the HI
register would always be adjacent to the LO register. With
VBIF 2.0, this assumption has now been broken, so both the
HI and LO register offsets must be returned.

CRs-fixed: 578771
Change-Id: Ie74da5d797e58a143b89a61aba7ebaf1ed42ed5e
Signed-off-by: default avatarKevin Matlage <kmatlage@codeaurora.org>
parent d906f72c

drivers/gpu/msm/a4xx_reg.h

+6 −1
Original line number Diff line number Diff line
@@ -130,12 +130,17 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_RBBM_CFG_DEBBUS_LOADIVT		0x95



#define A4XX_RBBM_PERFCTR_CP_0_LO		0x9c

#define A4XX_RBBM_PERFCTR_CP_0_HI		0x9d

#define A4XX_RBBM_PERFCTR_CP_1_LO		0x9e

#define A4XX_RBBM_PERFCTR_CP_1_HI		0x9f

#define A4XX_RBBM_PERFCTR_RBBM_0_LO		0xac

#define A4XX_RBBM_PERFCTR_RBBM_0_HI		0xad

#define A4XX_RBBM_PERFCTR_RBBM_1_LO		0xae

#define A4XX_RBBM_PERFCTR_RBBM_1_HI		0xaf

#define A4XX_RBBM_PERFCTR_RBBM_2_LO		0xb0

#define A4XX_RBBM_PERFCTR_RBBM_2_HI		0xb1

#define A4XX_RBBM_PERFCTR_RBBM_3_LO		0xb2



#define A4XX_RBBM_PERFCTR_RBBM_3_HI		0xb3

#define A4XX_RBBM_PERFCTR_PC_0_LO		0xb4

#define A4XX_RBBM_PERFCTR_PC_0_HI		0xb5

#define A4XX_RBBM_PERFCTR_PC_1_LO		0xb6

drivers/gpu/msm/adreno.c

+18 −6
Original line number Diff line number Diff line
@@ -603,7 +603,8 @@ int adreno_perfcounter_query_group(struct adreno_device *adreno_dev, 
}



static inline void refcount_group(struct adreno_perfcount_group *group,

	unsigned int reg, unsigned int flags, unsigned int *lo)

	unsigned int reg, unsigned int flags,

	unsigned int *lo, unsigned int *hi)

{

	if (flags & PERFCOUNTER_FLAG_KERNEL)

		group->regs[reg].kernelcount++;
@@ -612,6 +613,9 @@ static inline void refcount_group(struct adreno_perfcount_group *group, 


	if (lo)

		*lo = group->regs[reg].offset;



	if (hi)

		*hi = group->regs[reg].offset_hi;

}



/**
@@ -619,7 +623,8 @@ static inline void refcount_group(struct adreno_perfcount_group *group, 
 * @adreno_dev: Adreno device to configure

 * @groupid: Desired performance counter group

 * @countable: Countable desired to be in a counter

 * @offset: Return offset of the countable

 * @offset: Return offset of the LO counter assigned

 * @offset_hi: Return offset of the HI counter assigned

 * @flags: Used to setup kernel perf counters

 *

 * Try to place a countable in an available counter.  If the countable is
@@ -629,7 +634,7 @@ static inline void refcount_group(struct adreno_perfcount_group *group, 


int adreno_perfcounter_get(struct adreno_device *adreno_dev,

	unsigned int groupid, unsigned int countable, unsigned int *offset,

	unsigned int flags)

	unsigned int *offset_hi, unsigned int flags)

{

	struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;

	struct adreno_perfcount_group *group;
@@ -639,6 +644,8 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 
	/* always clear return variables */

	if (offset)

		*offset = 0;

	if (offset_hi)

		*offset_hi = 0;



	if (NULL == counters)

		return -EINVAL;
@@ -660,7 +667,8 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 
		/* If it is already reserved, just increase the refcounts */

		if ((group->regs[countable].kernelcount != 0) ||

			(group->regs[countable].usercount != 0)) {

				refcount_group(group, countable, flags, offset);

				refcount_group(group, countable, flags,

					offset, offset_hi);

				return 0;

		}
@@ -676,7 +684,8 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 


		for (i = 0; i < group->reg_count; i++) {

			if (group->regs[i].countable == countable) {

				refcount_group(group, i, flags, offset);

				refcount_group(group, i, flags,

					offset, offset_hi);

				return 0;

			} else if (group->regs[i].countable ==

			KGSL_PERFCOUNTER_NOT_USED) {
@@ -709,6 +718,8 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 


	if (offset)

		*offset = group->regs[empty].offset;

	if (offset_hi)

		*offset_hi = group->regs[empty].offset_hi;



	return ret;

}
@@ -2933,7 +2944,8 @@ static long adreno_ioctl(struct kgsl_device_private *dev_priv, 
		if (result)

			break;

		result = adreno_perfcounter_get(adreno_dev, get->groupid,

			get->countable, &get->offset, PERFCOUNTER_FLAG_NONE);

			get->countable, &get->offset, &get->offset_hi,

			PERFCOUNTER_FLAG_NONE);

		kgsl_active_count_put(device);

		break;

	}

drivers/gpu/msm/adreno.h

+2 −1
Original line number Diff line number Diff line
@@ -228,6 +228,7 @@ struct adreno_perfcount_register { 
	unsigned int kernelcount;

	unsigned int usercount;

	unsigned int offset;

	unsigned int offset_hi;

	int load_bit;

	unsigned int select;

	uint64_t value;
@@ -634,7 +635,7 @@ const char *adreno_perfcounter_get_name(struct adreno_device 


int adreno_perfcounter_get(struct adreno_device *adreno_dev,

	unsigned int groupid, unsigned int countable, unsigned int *offset,

	unsigned int flags);

	unsigned int *offset_hi, unsigned int flags);



int adreno_perfcounter_put(struct adreno_device *adreno_dev,

	unsigned int groupid, unsigned int countable, unsigned int flags);

drivers/gpu/msm/adreno_a3xx.c

+74 −58
Original line number Diff line number Diff line
@@ -1651,141 +1651,158 @@ static const struct adreno_vbif_platform a3xx_vbif_platforms[] = { 


static struct adreno_perfcount_register a3xx_perfcounters_cp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_CP_0_LO,

		0, A3XX_CP_PERFCOUNTER_SELECT },

		A3XX_RBBM_PERFCTR_CP_0_HI, 0, A3XX_CP_PERFCOUNTER_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_rbbm[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_0_LO,

		1, A3XX_RBBM_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_RBBM_0_HI, 1, A3XX_RBBM_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_1_LO,

		2, A3XX_RBBM_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_RBBM_1_HI, 2, A3XX_RBBM_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_pc[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_0_LO,

		3, A3XX_PC_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_PC_0_HI, 3, A3XX_PC_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_1_LO,

		4, A3XX_PC_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_PC_1_HI, 4, A3XX_PC_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_2_LO,

		5, A3XX_PC_PERFCOUNTER2_SELECT },

		A3XX_RBBM_PERFCTR_PC_2_HI, 5, A3XX_PC_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_3_LO,

		6, A3XX_PC_PERFCOUNTER3_SELECT },

		A3XX_RBBM_PERFCTR_PC_3_HI, 6, A3XX_PC_PERFCOUNTER3_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_vfd[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_0_LO,

		7, A3XX_VFD_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_VFD_0_HI, 7, A3XX_VFD_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_1_LO,

		8, A3XX_VFD_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_VFD_1_HI, 8, A3XX_VFD_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_hlsq[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_0_LO,

		9, A3XX_HLSQ_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_HLSQ_0_HI, 9,

		A3XX_HLSQ_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_1_LO,

		10, A3XX_HLSQ_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_HLSQ_1_HI, 10,

		A3XX_HLSQ_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_2_LO,

		11, A3XX_HLSQ_PERFCOUNTER2_SELECT },

		A3XX_RBBM_PERFCTR_HLSQ_2_HI, 11,

		A3XX_HLSQ_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_3_LO,

		12, A3XX_HLSQ_PERFCOUNTER3_SELECT },

		A3XX_RBBM_PERFCTR_HLSQ_3_HI, 12,

		A3XX_HLSQ_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_4_LO,

		13, A3XX_HLSQ_PERFCOUNTER4_SELECT },

		A3XX_RBBM_PERFCTR_HLSQ_4_HI, 13,

		A3XX_HLSQ_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_5_LO,

		14, A3XX_HLSQ_PERFCOUNTER5_SELECT },

		A3XX_RBBM_PERFCTR_HLSQ_5_HI, 14,

		A3XX_HLSQ_PERFCOUNTER5_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_vpc[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_0_LO,

		15, A3XX_VPC_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_VPC_0_HI, 15, A3XX_VPC_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_1_LO,

		16, A3XX_VPC_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_VPC_1_HI, 16, A3XX_VPC_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_tse[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_0_LO,

		17, A3XX_GRAS_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_TSE_0_HI, 17, A3XX_GRAS_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_1_LO,

		18, A3XX_GRAS_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_TSE_1_HI, 18, A3XX_GRAS_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_ras[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_0_LO,

		19, A3XX_GRAS_PERFCOUNTER2_SELECT },

		A3XX_RBBM_PERFCTR_RAS_0_HI, 19, A3XX_GRAS_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_1_LO,

		20, A3XX_GRAS_PERFCOUNTER3_SELECT },

		A3XX_RBBM_PERFCTR_RAS_1_HI, 20, A3XX_GRAS_PERFCOUNTER3_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_uche[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_0_LO,

		21, A3XX_UCHE_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_UCHE_0_HI, 21,

		A3XX_UCHE_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_1_LO,

		22, A3XX_UCHE_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_UCHE_1_HI, 22,

		A3XX_UCHE_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_2_LO,

		23, A3XX_UCHE_PERFCOUNTER2_SELECT },

		A3XX_RBBM_PERFCTR_UCHE_2_HI, 23,

		A3XX_UCHE_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_3_LO,

		24, A3XX_UCHE_PERFCOUNTER3_SELECT },

		A3XX_RBBM_PERFCTR_UCHE_3_HI, 24,

		A3XX_UCHE_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_4_LO,

		25, A3XX_UCHE_PERFCOUNTER4_SELECT },

		A3XX_RBBM_PERFCTR_UCHE_4_HI, 25,

		A3XX_UCHE_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_5_LO,

		26, A3XX_UCHE_PERFCOUNTER5_SELECT },

		A3XX_RBBM_PERFCTR_UCHE_5_HI, 26,

		A3XX_UCHE_PERFCOUNTER5_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_tp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_0_LO,

		27, A3XX_TP_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_TP_0_HI, 27, A3XX_TP_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_1_LO,

		28, A3XX_TP_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_TP_1_HI, 28, A3XX_TP_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_2_LO,

		29, A3XX_TP_PERFCOUNTER2_SELECT },

		A3XX_RBBM_PERFCTR_TP_2_HI, 29, A3XX_TP_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_3_LO,

		30, A3XX_TP_PERFCOUNTER3_SELECT },

		A3XX_RBBM_PERFCTR_TP_3_HI, 30, A3XX_TP_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_4_LO,

		31, A3XX_TP_PERFCOUNTER4_SELECT },

		A3XX_RBBM_PERFCTR_TP_4_HI, 31, A3XX_TP_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_5_LO,

		32, A3XX_TP_PERFCOUNTER5_SELECT },

		A3XX_RBBM_PERFCTR_TP_5_HI, 32, A3XX_TP_PERFCOUNTER5_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_sp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_0_LO,

		33, A3XX_SP_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_SP_0_HI, 33, A3XX_SP_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_1_LO,

		34, A3XX_SP_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_SP_1_HI, 34, A3XX_SP_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_2_LO,

		35, A3XX_SP_PERFCOUNTER2_SELECT },

		A3XX_RBBM_PERFCTR_SP_2_HI, 35, A3XX_SP_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_3_LO,

		36, A3XX_SP_PERFCOUNTER3_SELECT },

		A3XX_RBBM_PERFCTR_SP_3_HI, 36, A3XX_SP_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_4_LO,

		37, A3XX_SP_PERFCOUNTER4_SELECT },

		A3XX_RBBM_PERFCTR_SP_4_HI, 37, A3XX_SP_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_5_LO,

		38, A3XX_SP_PERFCOUNTER5_SELECT },

		A3XX_RBBM_PERFCTR_SP_5_HI, 38, A3XX_SP_PERFCOUNTER5_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_6_LO,

		39, A3XX_SP_PERFCOUNTER6_SELECT },

		A3XX_RBBM_PERFCTR_SP_6_HI, 39, A3XX_SP_PERFCOUNTER6_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_7_LO,

		40, A3XX_SP_PERFCOUNTER7_SELECT },

		A3XX_RBBM_PERFCTR_SP_7_HI, 40, A3XX_SP_PERFCOUNTER7_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_rb[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_0_LO,

		41, A3XX_RB_PERFCOUNTER0_SELECT },

		A3XX_RBBM_PERFCTR_RB_0_HI, 41, A3XX_RB_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_1_LO,

		42, A3XX_RB_PERFCOUNTER1_SELECT },

		A3XX_RBBM_PERFCTR_RB_1_HI, 42, A3XX_RB_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_0_LO,

		-1, 0 },

		A3XX_RBBM_PERFCTR_PWR_0_HI, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_1_LO,

		-1, 0 },

		A3XX_RBBM_PERFCTR_PWR_1_HI, -1, 0 },

};



static struct adreno_perfcount_register a3xx_perfcounters_vbif[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT0_LO, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT1_LO, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT0_LO,

		A3XX_VBIF_PERF_CNT0_HI, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT1_LO,

		A3XX_VBIF_PERF_CNT1_HI, -1, 0 },

};

static struct adreno_perfcount_register a3xx_perfcounters_vbif_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT0_LO, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT1_LO, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT2_LO, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT0_LO,

		A3XX_VBIF_PERF_PWR_CNT0_HI, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT1_LO,

		A3XX_VBIF_PERF_PWR_CNT1_HI, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT2_LO,

		A3XX_VBIF_PERF_PWR_CNT2_HI, -1, 0 },

};



static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {
@@ -1820,14 +1837,11 @@ static inline int _get_counter(struct adreno_device *adreno_dev, 
	int ret = 0;



	if (*lo == 0) {

		*hi = 0;



		ret = adreno_perfcounter_get(adreno_dev, group, countable,

			lo, PERFCOUNTER_FLAG_KERNEL);

			lo, hi, PERFCOUNTER_FLAG_KERNEL);



		if (ret == 0)

			*hi = *lo + 1;

		else {

		if (ret) {

			struct kgsl_device *device = &adreno_dev->dev;



			KGSL_DRV_ERR(device,
@@ -1937,15 +1951,17 @@ int a3xx_perfcounter_init(struct adreno_device *adreno_dev) 
	/* Turn on the GPU busy counter(s) and let them run free */

	/* GPU busy counts */

	ret = adreno_perfcounter_get(adreno_dev, KGSL_PERFCOUNTER_GROUP_PWR, 1,

			NULL, PERFCOUNTER_FLAG_KERNEL);

			NULL, NULL, PERFCOUNTER_FLAG_KERNEL);



	/* VBIF waiting for RAM */

	ret |= adreno_perfcounter_get(adreno_dev,

				KGSL_PERFCOUNTER_GROUP_VBIF_PWR, 0,

				NULL, PERFCOUNTER_FLAG_KERNEL);

				NULL, NULL, PERFCOUNTER_FLAG_KERNEL);



	/* VBIF DDR cycles */

	ret |= adreno_perfcounter_get(adreno_dev, KGSL_PERFCOUNTER_GROUP_VBIF,

				VBIF_AXI_TOTAL_BEATS,

				&adreno_dev->ram_cycles_lo,

				&adreno_dev->ram_cycles_lo, NULL,

				PERFCOUNTER_FLAG_KERNEL);



	/* Default performance counter profiling to false */

drivers/gpu/msm/adreno_a4xx.c

+96 −100

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