Loading arch/arm/boot/dts/qcom/msm8992.dtsi +13 −1 Original line number Diff line number Diff line Loading @@ -449,7 +449,19 @@ }; clock_mmss: qcom,mmsscc@fd8c0000 { compatible = "qcom,dummycc"; compatible = "qcom,mmsscc-8992"; reg = <0xfd8c0000 0x5200>; reg-names = "cc_base"; vdd_dig-supply = <&pm8994_s1_corner>; mmpll4_dig-supply = <&pm8994_s1_corner>; mmpll4_analog-supply = <&pm8994_l12>; clock-names = "xo", "gpll0", "mmssnoc_ahb", "oxili_gfx3d_clk", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src", "extpclk_src"; clocks = <&clock_rpm clk_cxo_clk_src>, <&clock_gcc clk_gpll0_out_mmsscc>, <&clock_rpm clk_mmssnoc_ahb_clk>, <&clock_rpm clk_oxili_gfx3d_clk_src>; #clock-cells = <1>; }; Loading Loading
arch/arm/boot/dts/qcom/msm8992.dtsi +13 −1 Original line number Diff line number Diff line Loading @@ -449,7 +449,19 @@ }; clock_mmss: qcom,mmsscc@fd8c0000 { compatible = "qcom,dummycc"; compatible = "qcom,mmsscc-8992"; reg = <0xfd8c0000 0x5200>; reg-names = "cc_base"; vdd_dig-supply = <&pm8994_s1_corner>; mmpll4_dig-supply = <&pm8994_s1_corner>; mmpll4_analog-supply = <&pm8994_l12>; clock-names = "xo", "gpll0", "mmssnoc_ahb", "oxili_gfx3d_clk", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src", "extpclk_src"; clocks = <&clock_rpm clk_cxo_clk_src>, <&clock_gcc clk_gpll0_out_mmsscc>, <&clock_rpm clk_mmssnoc_ahb_clk>, <&clock_rpm clk_oxili_gfx3d_clk_src>; #clock-cells = <1>; }; Loading